Browse Prior Art Database

DC Scan Diagnostic Method

IP.com Disclosure Number: IPCOM000021956D
Original Publication Date: 2004-Feb-17
Included in the Prior Art Database: 2004-Feb-17
Document File: 7 page(s) / 90K

Publishing Venue

IBM

Abstract

This article proposes a solution to the problem of testing and efficiently diagnosing DC (broken or stuck-at) scan chain defects and localizing these defects to a failing Shift Register Latch (SRL) or associated scan clock tree. This on-the-fly quick and accurate pinpointing of systematic and random circuit faults can be performed during the test process of most scan based designs.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 31% of the total text.

Page 1 of 7

DC Scan Diagnostic Method

This problem is usually encountered early in the technology's life cycle and is critical in improving the process so it quickly achieves manufacturing yield levels. An inability to improve the technology and yield can greatly impact a program or at least severely minimize the revenue that could be realized. Rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed to understand and correct the process anomalies. Background Information - Before describing the solution to the problem referenced above we shall give a short overview of the scan based design and test methodology. Specifically, we shall discuss the LSSD (Ref. 1-2) as practiced in most IBM chip and system designs, although many of the basic concepts apply to other variations of scan designs.

SR I

PIs PO s

S can clks

System clks

In a scan based design, the latches are accessible via serial access. This scan control can be implemented in several forms, a common implementation being LSSD. In such a design, most of the device's storage elements,such as latches or registers are concatenated in one or more scan chains and can be externally accessible via one or more serial inputs and outputs, see Fig. 1. LSSD latches are typically designed in a L1/L2 configuration where the L1 or master latch has two data ports and may be

updated by either a scan clock (A clock) or a functional system clock (C1 clock). The L2 or slave latch has a scan clock input (B clock) and the system clock (C2 clock) and these clocks are out of phase with both L1 clocks. Scanning is done using separate A and B clocks and chip testing uses C1 and C2 clocks, see Fig. 2. In most IBM high end microprocessor chips, STUMPs based LBIST is an essential. Fig. 3 shows the STUMPS based LBIST test scheme where pseudo random patterns are generated by PRPG and the test results are compressed into the MISR.

A major drawback of this test methodology is encountered when the scan chain is

taL c seh

acS C n niah

Combinational Logic Combinational Logic Combinational Logic

taL c seh

acS C n niah

SR O

Fig. 1 - Typical LS S D C onfiguration

1

[This page contains 2 pictures or other non-text objects]

Page 2 of 7

not functioning properly and access to the internal logic of the device is greatly reduced. This is often the case early in the technology or product introduction cycle when the yields are relatively low or zero. In these situations the rapid determination of the problem's root cause is critical, but not easily diagnosable. There are several techniques that have been used in the past to diagnose this type of failure with limited success (Ref. 3-8).

SRL1 SRL2 SRLn-1 SRLn

Fig. 2 - Typical LSSD Scan Chain

In these low or zero yield situations, the most common failure is often the scan chain. Albeit, the design must be a scan based design but this is very common and scan chains represent a significant portion of the real estate area. Having a solution which speeds DC diagnostics on...