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Plane Capacitance Reducing Slits for High-Speed IO Signals

IP.com Disclosure Number: IPCOM000022013D
Publication Date: 2004-Feb-18
Document File: 3 page(s) / 179K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that places slits or rectangular holes on the power and/or ground plane around the signal pads. The slits reduce lateral plane capacitance when the high-speed signals pass through vertical paths. Benefits include a solution that is simpler and less costly than the current state of the art.

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Plane Capacitance Reducing Slits for High-Speed IO Signals

Disclosed is a method that places slits or rectangular holes on the power and/or ground plane around the signal pads. The slits reduce lateral plane capacitance when the high-speed signals pass through vertical paths. Benefits include a solution that is simpler and less costly than the current state of the art.

Background

In package and PCB design, vertical transitions (such as via transitions) must be created carefully because there are no good return paths. Poor return paths cause high mismatching and poor return loss performances. In addition, in multi-layer structures, the parasitic capacitances arising from inter layers and from the signal pad to power/ground layers are significantly high, and deteriorate high-speed signal integrity. Simulation results show that Z0=sqrt(L/C) of the vertical path is lower than the system reference impedance, which is typically 50 ohms.

In practical design, making good return paths is too expensive to realize good vertical return paths. As an alternative, parasitic capacitances are reduced to increase the Z0 to an appropriate level for system impedance. Currently, the mismatching of vertical paths is solved by placing stitching vias between the power and ground planes (see Figure 1), and by increasing the void sizes of the power and ground planes around the signal pads. However, this solution increases costs, and the improvements in mismatching are limited because the capacitance...