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Modifying an SDRAM controller design to support attachment to SSRAM as well

IP.com Disclosure Number: IPCOM000022085D
Original Publication Date: 2004-Feb-23
Included in the Prior Art Database: 2004-Feb-23
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Abstract

Disclosed is a design for modifying a Synchronous Dynamic Random Access Memory (SDRAM) controller to support attachment to Synchronous Static Randon Access Memory (SSRAM) as well.

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Modifying an SDRAM controller design to support attachment to SSRAM as well

Disclosed is a technique for modifying an existing Synchronous Dynamic Random Access Memory (SDRAM) controller to handle not only the attachment of SDRAM devices but Synchronous Static Random Access Memory (SSRAM) devices as well. This allows the application to choose the memory type that best suits it. If cost is pre-eminent, then SDRAM devices may be the better choice. If performance is pre-eminent, then SSRAM devices may be the better choice. A typical memory controller will support only one memory type or the other, not both.

It is only necessary to add a single output pin to the original SDRAM controller design to support SSRAM. This is actually another vital ingrediant of this design --- it does not add significantly to the Application Specific Integrated Circuit (ASIC) cost since there is no significant increase in the ASIC's Input/Output (I/O) pin count to add this capability. This new output pin is intended to drive the chip select (CS#) input of the SSRAM. This output is asserted whenever the ASIC SDRAM controller state machine generates a Column Address Strobe (CAS#) cycle --- either a read or a write cycle. Note that the ASIC SDRAM controller CAS# pin itself could not be used for this purpose, since that pin is also asserted during refresh cycles. Another achievement of this design is the support of the attachment of SSRAM while at the same time adding only minimal complexity to an existing SDRAM controller design. This reduces the possibility of introducing logic design defects with this modification. Thus it is key that the SDRAM memory controller not even be aware to which type of memory it is actually attached ---
i.e. there is no need for modification to the ASIC SDRAM controller state machine sequences. The only modification required is to generate an additi...