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Method for pseudo-hidden memory refresh

IP.com Disclosure Number: IPCOM000022119D
Publication Date: 2004-Feb-25
Document File: 7 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for pseudo-hidden memory refresh. Benefits include improved performance and improved functionality.

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Method for pseudo-hidden memory refresh

Disclosed is a method for pseudo-hidden memory refresh. Benefits include improved performance and improved functionality.

Background

         Each memory cell in a dynamic random access memory (DRAM) is constructed from a single transistor and a single capacitor. The device is considered dynamic because its data decays and becomes invalid due to various leakage current paths to surrounding cells and to the substrate. To maintain the validity of the data, each memory cell is periodically refreshed. Additionally, each cell is refreshed every time it is read out of the array into the sense amplifiers and subsequently rewritten into the cell.

         The memory controller is responsible for periodically performing refresh maintenance operations on the memory cell array. Every row of the memory array must be refreshed before the data in the row decays to an invalid state.

         Refresh timing parameters include the following:

•         tREF= Refresh period. To ensure data integrity in DRAMs with 16K rows, 16K number of refresh commands must be executed to every bank within tREF period. A typical value is approximately 32 msec. For low latency specialty DRAMs, the tREF value is a smaller period than commodity DRAMs because the fast transistors used are more leaky and require frequent refreshing. The refresh period for low latency DRAM is in the range of 8-16 ms.

•         tRFC= Time to refresh a single row. This value is also the time interval between a refresh (REF command) to another REF command to different rows of the same bank. The tRFC value is smaller than tRC as column access gates are not turned on.

At end of tRFC, either a REF or activate command (ACT) can be stored in the bank refreshed.

         Refresh overhead can be calculated for a low latency 256-Mb DRAM with 8 banks of memory and 16K rows per bank. Each bank requires 16K refresh cycles that use tRFC (10 ns) each. The time to refresh a single bank is:

16384 x 10 ns= 163,840 ns= 0.16384 ms

The time required to refresh 8 banks is:

0.16384ms x 8= 1.31072 ms

         Assuming 8ms for the refresh period (tREF), the overhead required is:

Overhead = 0.6522 ms/8.0 ms = 16.384%

         As DRAM densities increase over time (256Mbità512Mbità1Gbit….), the trend is to utilize more rows of memory, which increases the refresh overhead.

         DRAM devices can be used for cache data memory instead of conventional static random access memory (SRAM) devices as DRAM latencies are approaching that of SRAMs. This usage results in significant cost savings and enables larger cache sizes as DRAMs have higher memory densities (256 Mb DRAM vs. 72 Mb SRAM). The DRAM device is also called high-speed DRAM cache (HDC).

         The downside of using DRAM devices rather than SRAMs is that DRAMs must be periodically refreshed. DRAM refresh overhead is significant, and the disclosed method reduces refresh overhead by performing refreshes in parallel with other DRAM accesses.

General description

         The disclosed method is pseudo-hidden DRAM memory re...