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Method for noninvasive monitoring and evaluating of a computer system and internal bus quality/reliability

IP.com Disclosure Number: IPCOM000022126D
Publication Date: 2004-Feb-25
Document File: 8 page(s) / 79K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for the noninvasive monitoring and evaluating of a computer system and internal bus quality/reliability. Benefits include improved functionality and improved test environment.

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Method for noninvasive monitoring and evaluating of a computer system and internal bus quality/reliability

Disclosed is a method for the noninvasive monitoring and evaluating of a computer system and internal bus quality/reliability. Benefits include improved functionality and improved test environment.

Background

The bit error rate (BER) is defined as:
“Measured BER” = N/(T x R)

The value N is the number of bits received in error. The value T is the Test Time (seconds). The value R is the link data rate (number of total bits received).

BER testing is conventionally conducted on high-speed communication links to assess the quality of the link and determine if the criteria for industry standard requirements are met. BER methodology is well suited for these types of applications because inherent noise, such as jitter and signal degradation over cables, exists in those environments.

In computer systems, BER can be affected by chip/board, system, and environmental parameters, including:

• Clock and strobe integrity

• Voltage variation

• Skew material

• Temperature variation

• I/O compensation circuitry

Significant analog testing is performed at the chip level and/or system level, including signal integrity analysis, timing verification, and system-level functional testing. Various stress conditions are tested, such as thermal, voltage margining and skewed part testing. However, no sustained testing is performed that measures analog quality and reliability, focusing on each individual bus that interfaces to chipsets in a complete computer system.

The requirement for the methodology has spawned a related test-equipment industry, such as BER pattern generators, receivers, and comparators. Other applications that use BER include chip testing at the chip level. With the expectation of errors in operating mode or in development, BER metrics establish a baseline for performance and a methodology for analyzing error data to verify and characterize designs.

Emerging technologies in high-speed bus design and anticipated material constraints result in increasingly acceptable bus errors. However, zero errors should be detected in all internal buses under environmental conditions spanning nominal to extreme boundaries within specifications. Testing beyond the established boundaries characterizes sensitivities.

General description

The disclosed method incorporates BER testing and analysis methodology into computer-system design and testing. The method augments conventional validation techniques to measure the quality and reliability of internal bus structures by establishing and verifying their BER standards.

The disclosed method includes a noninvasive diagnostic tool. Errors are correlated to specific data patterns and specific buses without using logic analyzers or scope probing. Software exists for monitoring parity or correction code errors using BER analysis techniques. As a result, the cost and mechanical constraints required for logic anal...