Browse Prior Art Database

Per-Thread Valid Bits for Virtually-Indexed Virtually-Tagged Caches

IP.com Disclosure Number: IPCOM000022178D
Original Publication Date: 2004-Mar-01
Included in the Prior Art Database: 2004-Mar-01
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Abstract

Providing a valid bit for each hardware thread in a multi-threaded CPU with virtually indexed, virtually tagged caches, allows cache lines to be simultaneously shared by multiple threads, improving performance.

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Per-Thread Valid Bits for Virtually-Indexed Virtually-Tagged Caches

A design is disclosed for allowing multiple cache lines to be shared by multiple threads in a virtually indexed, virtually tagged cache.

     A virtually indexed, virtually tagged cache requires no address translation during access, as both set selection (indexing) and tag compare are based on the virtual address. A common design in the presence of multi-threading is to tag lines by both hardware thread ID and virtual address. However, this allows a particular physical address to be in the cache only once. When two threads access the same physical address, the line will be repeatedly flushed from the cache and reloaded to change the hardware thread ID. This condition seriously degrades performance in the common case where multiple threads execute in the same address space.

     By providing a valid bit for each hardware thread in the tag, rather than a hardware ID, the same cache line can be shared by multiple hardware threads. Each cache line has a valid bit per thread. A line in the cache will only be used if the virtual address matches, and the correct valid bit is set. If multiple valid bits are set, then multiple threads will share the line. Shared lines are no longer flushed and reloaded, improving performance.

     Upon a miss, if a line was found with the correct virtual address, but without the appropriate valid bit set, this line becomes a candidate for sharing. When the miss is satisfied, if the cand...