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Per-Thread Valid Bits for Multithreaded Effective to Real Address Translation (ERATs)

IP.com Disclosure Number: IPCOM000022179D
Original Publication Date: 2004-Mar-01
Included in the Prior Art Database: 2004-Mar-01
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Abstract

Providing a valid bit for each hardware thread for each entry of a translation look-aside buffer allows entries to be simultaneously shared by multiple threads, improving processor performance.

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Per-Thread Valid Bits for Multithreaded Effective to Real Address Translation (ERATs)

A design is disclosed for allowing translation look-aside buffer (TLB) entries to be shared by multiple threads in a multi-threaded processor.

     A TLB is accessed by virtual address, and produces a translation, which contains the corresponding physical address and mode and status bits. A TLB is a cache of frequently used translations. When multiple hardware threads share a TLB, the TLB must track which translations belong to which thread, as the translations may be different in general. A common design is to tag each TLB entry with the hardware thread identifier with which the entry is associated. If multiple threads have identical translations, the same virtual address, physical address and mode bits, then these entries will be duplicated, reducing the effective size of the address translation table.

     In the disclosed design, each TLB entry has a valid bit per hardware thread, rather than a single hardware thread identifier. A thread can only use a TLB entry if the valid bit for that thread is set. This allows multiple threads to use the same entry, when multiple threads have the same translation. This increases the effective size of the TLB, reduces the number of TLB misses, and improves performance. One possible mechanism for setting multiple valid bits for a TLB entry is described below.

     Upon accessing the TLB, if a TLB entry is found with the correct virtual address, but the a...