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Method for a FBD logic analyzer interface

IP.com Disclosure Number: IPCOM000022263D
Publication Date: 2004-Mar-03
Document File: 7 page(s) / 248K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a fully buffered dual inline memory module (FBD) logic analyzer interface. Benefits include improved functionality and improved performance.

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Method for a FBD logic analyzer interface

Disclosed is a method for a fully buffered dual inline memory module (FBD) logic analyzer interface. Benefits include improved functionality and improved performance.

Background

         The following acronyms appear below:

•         DIMM – Dual inline memory module

•         FBD – Fully buffered DIMM

•         LA – Logic analyzer

•         LAI – Logic analyzer interface

•         SMB – System Management Bus

•         LCP – Liquid Crystal Polymer

         The FBD memory bus architecture requires traffic monitoring on a memory channel for system debugging. No conventional solution exists.

         Conventional memory probes have rigid assemblies. The memory connector designed into the basic LAI is assembled to a rigid base assembly. Th approach poses a number of restrictions and limitations on the use of the LAIs. For example, an LAI with a memory connector placed in line or parallel to the base card has an excessive overall height, usually two times or more great than the height of a standard DIMM card. This design may be acceptable for memory-down applications. The memory connectors are placed directly down on the motherboard and no other system components interfere with a tall FBD LAI interposer inserted into the DIMM connector (see Figure 1). However, where memory is placed on riser cards that face the same direction or face each other, interferences occur. Memory observability may be partial or selective or not observable at all (see Figure 2).

         When an LAI has a memory connector that extends at right angles to the base card (see Figure 3), the DIMM card resides at right angles to the LAI over the top of adjacent DIMM slots. If two to four adjacent slots require simultaneous probing, the LAI DIMM cards interfere with each other and only some of the bus is observable.

         A solution with full observability of the SMBus and memory is required.

General description

         The disclosed method is an LAI card that is interposed between a memory connector of an FBD link (channel) and a DIMM card, which plugs into the connector on the LAI card.

Advantages

         Some implementations of the disclosed structure and method provide one or more of the following advantages:

•         Improved functionality due to providing full observability for the SMBus and memory for analyzing, debugging and validating FBD memory traffic within a platform

•         Improved functionality due to enabling rotation of the DIMM to a multitude of configurations and gaining a much higher attach rate to the majority of systems requiring debug

•         Improved performance due to preventing the cables from prohibiting airflow cooling or the installation of other LAI probes

Detailed description

         The disclosed method is an LAI memory card for analyzing, debugging and validating FBD memory traffic within a platform. The method is comprised of the following components (see Figure 4):

•         3-Part board assembly

•         Bus repeater

•         FBD memory connector

•         Several circuits, including a clock and Vregs

•         Several egress cabl...