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XScale/ME Data Synchronization Mechanism for IXP2xxx Family of Network Processors

IP.com Disclosure Number: IPCOM000022271D
Publication Date: 2004-Mar-03
Document File: 4 page(s) / 21K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a locking mechanism, supported by SRAM and SCRATCH memory hardware, to perform data access synchronization between microengines (ME) and XScale. Benefits include reducing the complexity of network processor applications.

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XScale/ME Data Synchronization Mechanism for IXP2xxx Family of Network Processors

Disclosed is a method that uses a locking mechanism, supported by SRAM and SCRATCH memory hardware, to perform data access synchronization between microengines (ME) and XScale. Benefits include reducing the complexity of network processor applications.

Background

The IXP2xxx family of network processors (NP) can handle all types of network applications with the highest performance. The network processors contain a general-purpose processor that handles the slow data path of the network traffic, and a number of custom processors dedicated to handling of the fast path of the network traffic, called microengines (ME). The microengines are primarily responsible for handling network packets.

MEs are specialized processors with a limited amount of storage dedicated to executable code, so the XScale part of the NP is needed in the entire system setup and the handling of the slow data path, which usually consists of packets that can not be handled by the MEs and are sent to XScale for processing. Consequently, there are many interactions between the XScale core and MEs, including concurrent access to common data structures residing in SRAM, DRAM or SCRATCH memory.

If the XScale and the MEs try to access and modify concurrently the same memory location, the result could be a catastrophic system failure.

General Description

Disclosed is a method that uses a locking mechanism, supported by SRAM and SCRATCH memory hardware, to perform data access synchronization between MEs and XScale. Both XScale and MEs can perform atomic set/clear and atomic test_and_set/test_and_clear operations for both SRAM and SCRATCH memory. These atomic operations will set or clear the bits - that correspond to the bits set in the second operand - in the 32 bit word at the address passed as the first operand, and for the “test” versions will return the pre-modified value at the passed address. Based on these operations, an XScale/ME lock is implemented for each bit of an SRAM or SCRATCH memory location.

If the bit is set (1), then the lock is available. A test_and_clear operation for the bit clears the bit, and returns the previous...