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Method for a distributed design for an in-place debug system

IP.com Disclosure Number: IPCOM000022474D
Publication Date: 2004-Mar-17
Document File: 5 page(s) / 155K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a distributed design for an in-place debug system. Benefits include improved functionality and improved performance.

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Method for a distributed design for an in-place debug system

Disclosed is a method for a distributed design for an in-place debug system. Benefits include improved functionality and improved performance.

General description

         The disclosed method is a distributed design for an in-place debug system. The method improves silicon testing and validation by enabling observability over virtually any internal chip logic signal, in real-time. The method provides limited controllability of the clock circuitry of the chip.

         The system is collocated with the chip’s power domains but is independent of its logic and clocks. The debug system is purely combinatorial and is built as a distributed OR-chain. The interface to the system can be either dedicated or multiplexed on an existing interface. The system is designed to enable the debugging of the part while still in a reset state.

Advantages

         The disclosed method provides advantages, including:

•         Improved functionality due to providing an in-place debug system

•         Improved functionality due to providing a clock-stopping option that localizes a specific timeframe so that further testing can be carried out using scan circuits

•         Improved performance due to providing relative timing information between signals

•         Improved performance due to providing logic debug and performance monitoring functions via the bus snoopers while the device is out of reset

Detailed description

         The disclosed method enables the simultaneous observation of up to 16 bits of logic. They might be made of internal signals arising from functional unit blocks (FUBs) or bus-events condensed into one hot-signal. Each channel occupies one I/O pad that is unavailable for other purposes while utilizing the disclosed method. The pads should be output only. Programming for the disclosed method is done through the joint technical activities group (JTAG) interface. Other options include a dedicated interface and a software-controlled programming option.

         The disclosed method is divided into three functional modules: doorstep unit (DU), bus-snooper unit (BSU) and the pin interface block (PIB, see Figure 1).

Doorstep unit

         The DU is a 2-stage multiplexer/demultiplexer (MUX/DEMUX) that assigns an observable signal that is the target for the debug out of 32 candidates to one of 16 output channels. Each DU can select and map four observables. The selection and mapping are based on user programming. The state information is stored in registers that are clocked by the JTAG clock circuitry that are independent of the chip’s on-board logic. Barring the incremental load presented to the logic drivers, the DU is invisible to the functional units. Up to 64 DUs can be present in the debug system. The reset state defaults all doorsteps to no-visibility status (see Figure 2).

Bus-snooper unit

         The BSUs are...