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Circuit for an Automated On-Die Low Yield Analysis Test Mode of Memory Arrays

IP.com Disclosure Number: IPCOM000022483D
Publication Date: 2004-Mar-17
Document File: 4 page(s) / 704K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to characterize individual SRAM cells in microprocessor memory; it enables individual transistors in memory to be curve-traced at speed, and in parallel, on the die. Benefits include reducing test times and costs, and a measurement technique that can be used on future processes.

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Circuit for an Automated On-Die Low Yield Analysis Test Mode of Memory Arrays

Disclosed is a method to characterize individual SRAM cells in microprocessor memory; it enables individual transistors in memory to be curve-traced at speed, and in parallel, on the die. Benefits include reducing test times and costs, and a measurement technique that can be used on future processes.

Background

Low Yield Analysis (LYA) test mode is the most extensively used diagnosis technique in the fault isolation and failure analysis of memory cells. This technique provides information about the nature and strength of each transistor in SRAM memory by measuring the cell current from the pads. This is performed by placing a curve-tracer at the pads, and a large pass gate mux tree to allow access to any desired cell. Each memory cell is subjected to two curve-tracings; one with the word line on and the other with the word line off. The latter gives the leakage current in that path, which is then subtracted to get the final curve of the transistor under test. As the device feature shrinks, the leakage current increases by several times. This increased leakage current along with the distortion makes it almost impossible to detect the fault in the memory cell for future processes. This leakage is believed to further increase in the next generation process, thereby making this technique unusable. Also the number of memory cells on a chip keeps increasing, thereby increasing testing time and cost.

General Description

The disclosed method uses an On-Die Low Yield Analysis (ODLYA) circuit, along with the traditional LYA, to detect faults in the memory cell (see Figure 1). Distortion affecting the true curve is overcome by moving the fault detecting circuit on-die. This on-die feature places the measurement circuit closer to the memory cells, thereby reducing the pad and mux tree leakage and making the technique process independent to a large extent. On-die placement also helps in testing multiple memory cells in parallel, saving test time and cost.

In the ODLYA technique, the voltage is a set constant in one arm (either the BL or the BL#), and the current on the other arm is swept. The corresponding voltage is then measured. The cell pre-charge condition is decided by the transistor under test. For example, if the transistor m5 in Figure 2 is to be curve-traced, then the BL arm is maintained at a constant voltage of Vcc to turn on the NMOS. The current on the BL# is then swept using the PMOS cascode current mirror. This current produces a voltage that is then digitized using the fla...