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Performance Data Snarf of MESI Shared And Exclusive Data

IP.com Disclosure Number: IPCOM000022666D
Publication Date: 2004-Mar-25
Document File: 4 page(s) / 16K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that combines the performance data "snarf" of Modified Exclusive Shared Invalid (MESI) data "snarf" to increase system performance.

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Performance Data Snarf of MESI Shared And Exclusive Data

Disclosed is a method that combines the performance data “snarf” of Modified Exclusive Shared Invalid (MESI) data “snarf” to increase system performance.

Background

In order to maintain cache coherency, agents in muti-processor systems must own the data before they are modified. At times, other Front-side-bus (FSB) agents own the data or have a modified version of the data in their private cache.

The agent acquires the data by using a read for ownership cycle. Since all the agents in a coherent system need to monitor all the data transfers on the FSB, the agent that has modified the data interrupts the requesting agent’s cycle and indicates that the most recent copy of the data resides in its cache. This signal is a cache hit to a modified line. Instead of getting the data from memory, the agent that modified the data drives the modified data onto the FSB, and the agent that is requesting the data “snarfs” it directly from the FSB. The original agent that modified the data no longer owns the data; this agent marks the cache line invalid.

The agent that just “snarfed” the data owns it, and that cache line is in the exclusive state. Since the agent that performed the read for ownership intends to modify the data, the data will transition from the exclusive state to the modified state when the data is modified. Ownership of the cache line is transferred from one FSB agent to another. Typically, at this point the north bridge forwards the modified data that the first agent drove on the FSB to the memory controller. The memory controller then writes the modified data into memory. This type of cycle is required to maintain cache coherency in a multiprocessor system.

In newer multiprocessor system, the process follows the same steps until the north bridge forwards the data to the memory controller. The performance improvement arises if the cycle ends when the data is “snarfed” on the FSB. Though the data was not written to memory, the system still has one copy of the data that is current. The performance increase is a result of not using any memory bandwidth for writing the data to memory.

General Description

In the disclosed method, the performance data “snarf” of MESI shared and the exclusive data “snarf” are done to increase system performance, ( Substitute this for the first part of the sentence “In the disclosed method, the performance data “snarf” of MESI shared and exclusive data i...