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Improving Bit Error Events on High Speed Link Interconnects

IP.com Disclosure Number: IPCOM000022669D
Publication Date: 2004-Mar-25
Document File: 2 page(s) / 14K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that improves the observing and reporting of single bit errors on high-speed serial links. Benefits include a solution that addresses problems at the link level.

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Improving Bit Error Events on High Speed Link Interconnects

Disclosed is a method that improves the observing and reporting of single bit errors on high-speed serial links. Benefits include a solution that addresses problems at the link level.

Background

As serial link speeds increase, maintaining error-free link transmissions decreases. In PCI-express environments, the Bit Error Rates (BER) are about e-12, and on CSI-based systems it is approximately e-14 or e-15.

A high-speed serial interconnect approach to improving the observed link errors is to implement error correcting in the event of single/ multi bit errors, and by retrying the transmission known as Link Level Retry. However, this solution excludes certain design environments, such as the fault tolerant design based on lockstep operation. The lockstep operation cannot tolerate any event that causes a loss of the lockstep. Error correction or Link Level Retry is one source for the loss of lockstep. In such design environments, the allowable system down time, or number of events that causes one node to encounter error, is extremely limited. OEMs are targeting bit error rates better than e-22.

General Description

The disclosed method implements redundant links operating in a full- or semi-lockstep fashion across the interconnect, and transmits the same packet over both links at all times (see Figure 1). The Link Level Retry is turned off and no error correction is performed on the received packets.

At the receiver, the...