Browse Prior Art Database

Method for false-lock avoidance in a DLL

IP.com Disclosure Number: IPCOM000022670D
Publication Date: 2004-Mar-25
Document File: 3 page(s) / 19K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for false-lock avoidance in a delay-locked loop (DLL). Benefits include improved functionality, improved reliability, and improved design simplicity.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Method for false-lock avoidance in a DLL

Disclosed is a method for false-lock avoidance in a delay-locked loop (DLL). Benefits include improved functionality, improved reliability, and improved design simplicity.

Background

         DLLs are conventionally designed to produce a certain delay, which is precise and independent of process variation. The DLL receives a reference clock and locks on it. When the DLL is locked, a delay line made of inverters is tuned to have a delay equal to one-half a cycle of the reference clock. To lock, the DLL has a phase detector that compares the rising edge of the reference clock and the falling edge of the clock after the delay line (see Figure 1).

         A well-known problem with DLL locking is the false lock situation. Because the reference clock used for the DLL is periodical, the delay line can potentially produce a delay equal to 1.5 times the cycle time with the rising and falling edges remaining aligned. With a false lock, the DLL is locked on a delay equal to (0.5+n)*cycle_time, where n =1,2,3… (see Figure 2).

         The first step conventionally taken to avoid a false lock is to set the DLL’s initial conditions so that the DLL converges to the appropriate delay. However, the possibility of process variations remains, and changes in the reference clock frequency can cause bad initial conditions that end in a false lock.

         The second step taken to prevent a false lock is masking the reference clock at a rate of (k-1) cycles every k cycles. When the DLL is properly locked, the delay line produces a half-cycle delay period, which is the delay from the rising edge to the falling edge of the masked clock. For a false lock to occur, the delay line must produce a delay of (0.5+k)*cycle_time, which is less likely to happen. Using higher value for k improves the DLL’s immunity but also slows the cycle period down, so a limit exists for how high the value for k can be.

         A problem with the conventional solution is that it requires the reference clock to be stable when the DLL starts the locking process. On system power-up, the clock frequency, which is typically generated by a phase-locked loop (PLL), has a lot of variance. It can cause the DLL to have a false lock even when masking the clock. As a result, the DLL locking process should be started only after the clock is stable. However, applications require the locking process to be started at power-up without a stability delay.

General description

         This disclosed method prevents a false lock in a DLL and enable...