Browse Prior Art Database

A Cache Coherence Mechanism to Forward Clean Lines

IP.com Disclosure Number: IPCOM000022686D
Publication Date: 2004-Mar-25
Document File: 7 page(s) / 27K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a cache coherence mechanism that enables better data access latency on the shared bus, and can be implemented as part of an on-chip multiprocessor.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 27% of the total text.

A Cache Coherence Mechanism to Forward Clean Lines

Disclosed is a method for a cache coherence mechanism that enables better data access latency on the shared bus, and can be implemented as part of an on-chip multiprocessor.

Background

Multi-processors are usually designed with a mechanism for cache coherence. It is common for multiprocessors to provide cache-to-cache transfers, due to a snoop probe finding a line in another processor’s cache in the modified state. Cache-to-cache transfers result in an access latency typically half that of the transfer from the memory controller. The data return latency for a memory controller return is about 100-200 CPU cycles. The data return latency for a cache-to-cache transfer is about 50-60 CPU cycles.

General Description

The disclosed method uses a cache coherence mechanism that extends the cache-to-cache transfers to exclusive and shared lines, according to the Modified Exclusive Shared Invalid (MESI) cache coherence protocol. The cache coherence mechanism limits the data forwarding to be from a higher-level cache that has a lower utilization. This improves the overall shared bus access latency for applications with intensive data sharing.

The cache coherence mechanism introduces a new signal in the snoop phase on the shared
bus— a signal that indicates the snoop found a unique clean line that will result in a cache to cache transfer; this signal is used to identify a situation when a processor provides cache-to-cache transfer data for the transaction. The unique clean line signal is used in addition to the signals that find clean and modified lines required for the snoop phase.

In the disclosed method’s cache coherence mechanism, a transaction on the shared bus consists of various phases. Table 1 provides a description for these phases.

Phase

Description

 

 

Arbitration

Multiple processors arbitrate for ownership of the request/address bus

Request

The processor owning bus provides information regarding request

Snoop

Each processor posts clean and/or modified line snoop information for the request issued. The priority agent can request a deferral of the transaction by asserting the signal that indicates a transaction will not be serviced in order. Each processor also posts “non-modified data available for transfer” information.

Response

Responding agent provides response related to transaction

Data

Data transfer takes place in this phase

Deferred

Data is provided by the Memory/Node-controller in this phase, if the data is not available in any of the processors on the shared-bus.

Table 1. Different phases for each transaction on the shared bus

The clean line signal is driven by all the processors during the snoop phase to inform that a non-modified copy exists in its caches. The clean line signal is not asserted if it owns a modified copy, or if the request is invalid. There is another signal, the unique clean line (data transfer hit) that is being driven during this phase. A processor drives the...