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Method and apparatus for reducing logic activity during high-speed scan chain operation

IP.com Disclosure Number: IPCOM000022689D
Original Publication Date: 2004-Mar-25
Included in the Prior Art Database: 2004-Mar-25
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Abstract

Disclosed is a method and apparatus for reducing logic activity during high-speed scan chain operation.

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Method and apparatus for reducing logic activity during high -speed scan chain operation

Disclosed is a method and apparatus for reducing logic activity during high-speed scan chain operation. To avoid physical damage to chips due to excessive power dissipation, scan chains are often operated at lower than chip operating frequency. This may be necessary because scan chain operation causes large amounts of data swings in logic due to the simultaneous pseudo-random switching of data inputs to logic circuitry.

However, test time is an important contributor to the manufacturing cost of a chip. It is therefore desirable to allow scan chain operation at high frequency to reduce test time.

According to the present invention, logic activity is reduced to enable aggressive at-speed scan testing using transition barrier logic. This logic is specifically configured to freeze one input pattern to logic circuitry while the scan chain operates. This logic is used in conjunction with the scan-in and scan-out mode of operation of a chip, and deactivated during normal operation of the chip.

In a first exemplary embodiment, there is added output gating logic the latch, e.g., by inserting an AND gate to pull the output to constant low (0), or an OR gate to switch the output to constant high (1). While this design choice implies a small delay penalty due to transition barrier gate, barrier gate can be merged with other logic to reduce this penalty to 2 devices in a stack.

Scan latch...