Browse Prior Art Database

INTEGRATED MICROCIRCUIT WITH ON-CHIP LATCH

IP.com Disclosure Number: IPCOM000022858D
Original Publication Date: 1976-Mar-31
Included in the Prior Art Database: 2004-Mar-27
Document File: 2 page(s) / 288K

Publishing Venue

Xerox Disclosure Journal

Abstract

This circuit is a random access memory with a capacity of 32 words X 2 bits/word, The device has five address inputs ~ two write enable inputs (W01W1), an enable input (RE), a write control input (C), two data inputs (DO,Dl), a latch control input (L), and two outputs (BO,Bl), ~ functional diagram is shown above,

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Page 1 of 2

XEROX DISCLOSURE JOURNAL

INTEGRATED MICROCIRCUIT

WITH ON~CHIP L.~TCH
H. Y, Ho

Proposed Classification
U.S. Cl, 340/173
mt. Cl, Glic 11/44

D 0

wo

C

w~

This circuit is a random access memory with a capacity
of 32 words X 2 bits/word, The device has five address
inputs ~ two write enable inputs (W01W1),
an enable input (RE), a write control input (C), two
data inputs (DO,Dl), a latch control input (L), and two
outputs (BO,Bl), ~ functional diagram is shown above,

When ~E (device enable) is at logic high level the
device will be enabled and it will be possible to read
or write into the device, If ~E is at logic low level
the device will be disabled and, unless the outputs are
latched, they will remain at logic high level. Input C
is the write control input. When 2E is at logic high
level, and C is at logic low level, the device is in
the Write Mode, In the Write Mode, when enable W0 is
at logic low level the input data at D0 is written into
bit fo~~of the addressed word, If enable W1 is at logic
low level the input data at D1 will be written into bit

U]U

of the addressed word.

A0 A~A2 A3 A4

Volume 1. Number 3 March 1976 81

[This page contains 1 picture or other non-text object]

Page 2 of 2

INTEGRATED MICROCIRCUIT WITH ON-CHIP LATCH (Cont~d)

When the enable input, AE, is at a logic high level, and
the latch input, L, is at a logic high level, the device
is in the Read Mode. The outputs will then reflect the
contents of the addressed word,

When the latch input, L, is at a logic high level...