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MEMORY PARITY CHECKING

IP.com Disclosure Number: IPCOM000022868D
Original Publication Date: 1976-Mar-31
Included in the Prior Art Database: 2004-Mar-27
Document File: 2 page(s) / 219K

Publishing Venue

Xerox Disclosure Journal

Abstract

In a memory system having a plurality of memory modules 10, 12, 14, 16 each holding a portion of a single memory word 18a, 18b, l8c, l8d, respectively, a parity bit in each module is computed, at the time of storage, based on the parity of the next adjacent word portion. That is, parity bit 20a is the parity bit associated with word portion 18b, bit 2Db is associated with word portion 18c, bit 20c with word portion 18d and bit 20d with word portion 18a,

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XEROX DISCLOSURE JOURNAL

MEMORY PARITY CHECKING R, Vierson
L. Gorordo

Proposed Classification
U.S. Cl, 340/172,5
mt. Cl. G06f 1/00

In a memory system having a plurality of memory modules
10, 12, 14, 16 each holding a portion of a single memory
word 18a, 18b, l8c, l8d, respectively, a parity bit in
each module is computed, at the time of storage, based
on the parity of the next adjacent word portion. That
is, parity bit 20a is the parity bit associated with
word portion 18b, bit 2Db is associated with word
portion 18c, bit 20c with word portion 18d and bit 20d
with word portion 18a,

When a memory word is addressed through memory address
registers 22a, 22b, 22c, 22d, the addressed word seg~
ments are placed in registers 24a, 24b, 24c, 24d
respectively, together with the logically associated
parity bit from the adjacent word segment as described
above.

Parity of each word segment of registers 24 is computed
normally. In addition to the usual parity error
recognition, this technique ensures that the proper
word segment has been accessed from each memory
module.

Volume 1 Number 3 March 1976 79

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80 XEROX DISCLOSURE JOURNAL

Volume 1 Number 3 March 1976

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