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DUAL SPEED MICROPROCESSOR

IP.com Disclosure Number: IPCOM000023484D
Original Publication Date: 1977-Dec-31
Included in the Prior Art Database: 2004-Mar-31
Document File: 2 page(s) / 196K

Publishing Venue

Xerox Disclosure Journal

Abstract

A microprocessor 10 is capable of ope-ating at two different speeds of memory, e.g. a dynamic memory 12 at 0.5ps and a static memory 14 at l.5ps. A 4-stage counter 16 has its output connected to the microprocessor READY line. With the counter held in its reset state, the READY line will go high at the 0.5j-s rate, as determined by the counting cycle of the coun-ter. If the counter is allowed to run, the READY line will go high at a 2.Ojis rate, thereby establishing a 2.Ops cycle for the microprocessor. A l.5ps static memory can also operate at 2.0-is, The above time periods and number of counting stages are, of course, exemplary.

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XEROX DISCLOSURE JOURNAL

DUAL SPEED MICROPROCESSOR
ProposedGeorge L. Powers Classification

U.S. Cl. 340/172,5
Int. Cl, G06f 1/00

A microprocessor 10 is capable of ope~ating at two different
speeds of memory, e.g. a dynamic memory 12 at 0.5ps and a
static memory 14 at l.5ps. A 4-stage counter 16 has its output
connected to the microprocessor READY line. With the counter
held in its reset state, the READY line will go high at the
0.5j~s rate, as determined by the counting cycle of the coun-
ter. If the counter is allowed to run, the READY line will go
high at a 2.Ojis rate, thereby establishing a 2.Ops cycle for
the microprocessor. A l.5ps static memory can also operate at
2.0~is, The above time periods and number of counting stages
are, of course, exemplary.

Volume 2 Number 6 November/December 1977 95

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