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Method to Prevent Damage and Enhance Design Performance of Logic Analyzer Interface Probes for mPGA-Packaged Micro-Processors

IP.com Disclosure Number: IPCOM000023838D
Publication Date: 2004-Mar-31
Document File: 3 page(s) / 54K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a logic analyzer interface (LAI) probe assembly, an LGA/LGA-like connector, and a separate mPGA pin header. Benefits include enhanced design performance.

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Method to Prevent Damage and Enhance Design Performance of Logic Analyzer Interface Probes for mPGA-Packaged
Micro-Processors

Disclosed is a method that uses a logic analyzer interface (LAI) probe assembly, an LGA/LGA-like connector, and a separate mPGA pin header. Benefits include enhanced design performance.

Background

Currently, LAI probes for mPGA-packages processors contain a “pin-header” which is soldered to the bottom of the probe assembly (see Figure 1). This pin header is the probe’s interface to the processor socket on the system/board under test, and the pins on this header are arranged and spaced to match the same physical pattern and electrical assignments on the processor. Unfortunately, because the LAI probe assembly is bulky compared to the processor package, when the user attempts to install the probe into the processor socket, he/she cannot see the pins on the probe’s pin header. Without visual cues that affirm that the probe assembly is aligned correctly to the socket, the user often takes a “leap of faith” that everything is properly aligned when pressing/seating the probe into the socket; if the fragile (~ 12 mil in diameter) probe header pins are not properly aligned when the user takes this “leap of faith”, probe pin bending or breakage may occur; the pins are very small and bend easily, and there is little or no feedback that they are being damaged (see Figure 2). Pin damage causes validation downtime, requires time consuming and costly repairs of the probe, or permanent loss of the very expens...