Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

TRIGGERED PHASE-LOCK LOOP

IP.com Disclosure Number: IPCOM000023845D
Original Publication Date: 1979-Feb-28
Included in the Prior Art Database: 2004-Apr-01
Document File: 2 page(s) / 285K

Publishing Venue

Xerox Disclosure Journal

Abstract

A phase-1ock loop Circuit is disclosed for use in pulse systems such as a CRT deflection system, generalized communication channels, etc. The concept will be described for use in a CRT deflection system.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 67% of the total text.

Page 1 of 2

XEROX DISCLOSURE JOURNAL

TRIGGERED PHASE-~LOCKLOOP Proposed Classification ~ U.S. Cl. 33 1/20

mt. Cl. H03b 3/04

A phase~1ock loop Circuit is disclosed for use in pulse systems such as a CRT deflection system, generalized communication channels, etc. The concept will be described for use in a CRT deflection system.

Incoming signal A is applied to buffer 12 whose output signal B is applied simultaneously to phase comparator 22 and triggered oscillator 14. Therefore, triggered oscillator 14 is always synchronized to the incoming signal A, and lock of the triggered oscillator 14 is always ensured. Output C of triggered oscillator 14 is inputted to variable delay circuit 16. Output C of phase comparator 22 is inputted to the amplifier and filter 24 whose output H is inputted to the variable delay circuit 16 and serves to modulate the delay of the variable delay circuit 16, Output D of the variable delay circuit 16 is used to to drive the driver 18 whose output E drives the horizontal output stage 20. Output F of the output stage 20 is fed back into the phase comparator to close the loop.

The variable delay circuit 16 delays the signal so as to compensate for the delay of the output stage 20. The phase comparator 22 adjusts this delay for zero phase error. Since the triggered oscillator 14 is always locked to the sync (input signal
A), no jitter or loss of lock problems exist. This path can be wide band so that varying input frequencies can be easily locked to by the os...