Browse Prior Art Database

DIGITAL AUTOMATIC EQUALIZER

IP.com Disclosure Number: IPCOM000023927D
Original Publication Date: 1979-Apr-30
Included in the Prior Art Database: 2004-Apr-01
Document File: 4 page(s) / 624K

Publishing Venue

Xerox Disclosure Journal

Abstract

Disclosed is a hardware implementation of an all digital, eight-stagefrequency domain automatic equalizer employing a minimum mean-square-erroradjustment algorithm. The functional block diagram is illustrated in Figure L

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XEROX DISCLOSURE JOURNAL

~AL AU TOM AlICE UALIZER ProposedCarl Friedman Classification

U~S~CL 325/25 Int~CL H04b 13/00

SPARSE ~NVERSEO~SCRETE FOURIER TRANSFORM

OUTPUT

Volume 4 Number 2 March/April 1979 233

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DIGITAL AUTOMATIC EQUALIZER (ConVd)

   XEROX DISCLOSURE JOURNAL Volume 4 Number 2 March/April 1979

F/~2

234

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~iA~~UTOMATI~UALIZER (ConVd)

Disclosed is a hardware implementation of an all digital, eight~stagefrequency domain automatic equalizer employing a minimum mean~square~erroradjustment algorithm. The functional block diagram is illustrated in Figure L

The equalizer operates on eight samples of the input at one time. However, to facilitate output filtering, the input sample rate is doubled and the equalizer stores 16 samples and utilizes every alternate sample during each sample time. Thus, the sample storage register has 16 stages. During each sample time, one output sample is produced and then the sample set is updated by discarding the oldest sample and adding a new sample.

The Discrete Fourier Transform and subsequent frequency domain operations are conveniently depicted as parallel processes and have been partially implemented this way with analog circuits in earlier feasibility models. However, the speed of digital components allows for accomplishing serially the entire equalization function including initial automatic ad...