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TABLE LOOK-UP REALIZATION OF DIGITAL FILTERING

IP.com Disclosure Number: IPCOM000024286D
Original Publication Date: 1980-Feb-29
Included in the Prior Art Database: 2004-Apr-02
Document File: 2 page(s) / 105K

Publishing Venue

Xerox Disclosure Journal

Abstract

A digital, linear filter sequentially performs horizontal and vertical interpolation processes to achieve two-dimensional image scaling. To carry out the horizontal scaling, there is a shift register I1 for serially applying successive input sample sets or bytes to a table look-up memory or logic circuit 12. The shift register 11 and the table look-up memory or logic circuit 12 are preset under the control of anoperator controlled magnification and selection unit 13 so that the table look-up memory or logic circuit 12 provides Nk horizontally interpolated output bits in response to every n input samples, where k is horizontal scaling factor. Similarly, to perform the vertical scaling, there are a plurality of serially connected line length buffers 14-17 which are selectively brought on line under the control of a line buffer addition control unit 18 to simultaneously apply vertically aligned horizontally interpolated bits NK .(where j is a vertical scaling factor) of one or more successive scan lines to andther table look-up memory or logic circuit 19 via suitable storage registers 21-24, respectively. Again, the table look-up memory or logic circuits 19 provides n . horizontally interpolated bits. Those bits are output as a serial video data strea9 via an output buffer 25.

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Page 1 of 2

(EROX DISCLOSURE JOURNAL

TABLE LOOK-UP REALIZATION OF DIGITAL FILTERING
Henry Liao

Proposed Classification
U.S. C1. 358/280
Int. CI. H04n 1/40

SELECTION AND

1 2 12

HORIZONTAL TABLE LOOK-UP OR LOGIC

4 1 3 LINEBUFFER Pe

r

/I

19 u- VERTICAL +

TABLE LOOK-UP LINE BUFFER 2 OR LOGIC

I i (17

LINE BUFFER I

24

OUTPUT LINE BUFFER

3

VIDEO DATAOUT

A digital, linear filter sequentially performs horizontal and vertical interpolation processes to achieve two-dimensional image scaling.

To carry out the horizontal scaling, there is a shift register I1 for serially applying successive input sample sets or bytes to a table look-up memory or logic circuit 12. The shift register 11 and the table look-up memory or logic circuit 12 are preset under the control of anoperator controlled magnification and selection unit 13 so that the table look-up memory or logic circuit 12 provides Nk horizontally interpolated output bits in response to every n input samples, where k is horizontal scaling factor. Similarly, to perform the vertical scaling, there are a plurality of serially connected line length buffers 14-17 which are selectively brought on line under the control of a line buffer addition control unit 18 to simultaneously apply vertically aligned horizontally interpolated bits NK .(where j is a vertical scaling factor) of one or more successive scan lines to andther table look-up memory or logic circuit 19 via suitable storage registers 21-24, respectively. Again, the table look-up memory or logic circuits 19 provides n . horizontally interpolated bits. Those bits are output as a serial video data strea9 via an output buffer 25.

K

Volume 5 Number 1 January/February 1980 115

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TABLE LOOK-UP REALIZATION OF DIGITAL FILTERING (Cont'd)

The table l...