Browse Prior Art Database

HARDWARE IMPLEMENTATION OF 2 LINE/ll ELEMENT PREDICTOR

IP.com Disclosure Number: IPCOM000024488D
Original Publication Date: 1980-Oct-31
Included in the Prior Art Database: 2004-Apr-02
Document File: 2 page(s) / 86K

Publishing Venue

Xerox Disclosure Journal

Abstract

Data is usually compressed prior to transmission to reduce bandwidth, or prior to storage to reduce memory requirements. With a given set of text documents, the compression ratio can be improved if a suitably designed predictor operates on the data prior to the encoding steps.

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XEROX DISCLOSURE JOURNAL

HARDWARE IMPLEMENTATION OF 2 LINE/ll ELEMENT PREDICTOR Vinod K. Kadakia
Glen D. Jones

Proposed Classification
U.S. C1. 358/133 Int. C1. H04n 7/12

Data is usually compressed prior to transmission to reduce bandwidth, or prior to storage to reduce memory requirements. With a given set of text documents, the compression ratio can be improved if a suitably designed predictor operates on the data prior to the encoding steps.

The figure is a simplified schematic of a circuit required to predict four bits per clock period. The previous line buffer is a FIFO shift register (or equivalent) exactly one scan line minus eight bits long. In operation, four bit video nibbles are received on the current line and are shifted, in parallel, in one line through registers R2, R1 and RO, and in the other line, through the previous line buffer and registers LR4, LR3, LR2 and LR1. The latter line provides previous line data, and the former, current line data, to the address inputs of the four PROM's.

More specifically, for the previous line data, bits XI through X6, and for the current line data, bits X7 through Xl0 are supplied as ten address inputs to the Y1 PROM. The Xll bit is not suppled to the Y1 PROM. The Yl PROM output is two bits, one bit signifying the correct predictor if the Xll bit is one, the other the predictor output if the Xll bit is a zero.

Volume 5 Number 5 September/October 1980 54 1

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