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FIELD SHEILD FOR REDUCTION OF PARASITIC PERIPHERAL CAPACITANCE IN MOS DEVICE

IP.com Disclosure Number: IPCOM000024507D
Original Publication Date: 1980-Dec-31
Included in the Prior Art Database: 2004-Apr-02
Document File: 2 page(s) / 88K

Publishing Venue

Xerox Disclosure Journal

Abstract

For maximum sensitivity in a,n MOS circuit, including a charge-detection circuit, the capacitance of the sense transistor gate (node) must be minimized. An important contribution to the capacitance is the peripheral capacitance formed where the node dopant meets the field implant in the self-aligned field im plan t/oxide process.

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Page 1 of 2

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FIELD

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\ 1 DOPING PROFILE // ' - FIELD I MPLANT

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'REGION OF OVERLAP OF TWO

PROFILES CAUSING ABRUPT PN JUNCTION AND HIGH CAPACITANCE

POLY-SILICON FIELD KATE

FIELD

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COPING PROF

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PROFILE

For maximum sensitivity in a,n MOS circuit, including a charge-detection circuit, the capacitance of the sense transistor gate (node) must be minimized. An important contribution to the capacitance is the peripheral capacitance formed where the node dopant meets the field implant in the self-aligned field im plan t/oxide process.

Volume 5 Number 6 November/December 1980 583

[This page contains 1 picture or other non-text object]

Page 2 of 2

FIELD SHIELD FOR REDUCTION OF PARASITIC PERIPHERAL CAPACITANCE IN MOS DEVICE (Cont'd)

The basic concept is to use. a poly-silicon electrode to create lateral separation between node diffusion and field implant in an MOS self-aligned-gate process. The accompanying drawings compare diffusion profile cross-sections for the standard process (prior art) with the new process.

The edge of the node doping (n' , typically phosphorus or arsenic in an NMOS process) is determined by the edge of the field oxide in the standard process, Figure
1. Since the edge of the field implant is also determined by the same field oxide edge, there is unavoidably a region of overlap between the two doping profiles. This overlap causes an abrupt pn junction, which...