Browse Prior Art Database

NON-INTEGER INTERPOLATION WITH PARALLEL PIXEL DELETE

IP.com Disclosure Number: IPCOM000024607D
Original Publication Date: 1981-Apr-30
Included in the Prior Art Database: 2004-Apr-02
Document File: 2 page(s) / 79K

Publishing Venue

Xerox Disclosure Journal

Abstract

In electronic imaging it is often desirable to produce an output with a pixel spatial sample rate different from that of the input. Pixel throw-away can be used to produce an output with fewer pixels per inch; linear interpolation can be used to provide increased sample rate. Simple digital interpolation provides integer multiplication of the input rate. Thus, some combination of integer multiplication and pixel throw-away must be used to provide non-integer rate changes. Pixel throw-away is usually accomplished with a digital rate multiplier acting on the pixel clock. In the arrangement proposed herein, a parallel pixel throw-away is used to provide enhanced circuit simplicity and stability.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 72% of the total text.

Page 1 of 2

I

Int. CI. H04n 1/40

/

/9

PIXEL 2 PIXEL 3 PIXEL 6 PIXEL 9

                                           PIXEL I PIXEL 4 PIXEL 5 PIXEL 8 In electronic imaging it is often desirable to produce an output with a pixel spatial sample rate different from that of the input. Pixel throw-away can be used to produce an output with fewer pixels per inch; linear interpolation can be used to provide increased sample rate. Simple digital interpolation provides integer multiplication of the input rate. Thus, some combination of integer multiplication and pixel throw-away must be used to provide non-integer rate changes. Pixel throw-away is usually accomplished with a digital rate multiplier acting on the pixel clock. In the arrangement proposed herein, a parallel pixel throw-away is used to provide enhanced circuit simplicity and stability.

Referring to the Figure, pixels (i.e., 5 bits/pixel video) are input to one pixel delay buffer 6 and to one input (B) of adder 7 of interpolator section 4, and through line 3 to one input of threshold circuit 8. The output of buffer 6 is fed to a second input
(A) of adder 7. The output of adder 7 is fed to one input of a second threshold circuit 9. A digital threshold value, derived from a suitable source, is applied to a second input of threshold circuits 8, 9 through line 10.

The outputs of threshold circuits 8, 9 are fed to serial-to-parallel registers 12, 13 for real and interpolated pixels, respectively. The output terminals of registers 12, 13 are coupled to the output in a select...