Browse Prior Art Database

IMAGE SCALING USING BIT THROW-AWAY MEMORY

IP.com Disclosure Number: IPCOM000024634D
Original Publication Date: 1980-Dec-31
Included in the Prior Art Database: 2004-Apr-02
Document File: 2 page(s) / 93K

Publishing Venue

Xerox Disclosure Journal

Abstract

To implement image reduction in electronic imaging systems, a pixel throw-away is ordinarily used. Large Scale Integrated (LSI) circuits work well for this applicationwithin certain limits. Two difficulties which exist, however, are that the Transistor Transistor Logic (TTL) Binary Rate Multipliers (BRMs) presently available will not work at high data rates (i.e., 25 MHz is a typical maximum) and some applications require that not only the number of pixels to be deleted be known but also require that the pixels to be deleted be identified. While the BRM approach behaves precisely, it is difficult to calculate before hand exactly which pixels are to be deleted.

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IMAGE SCALING USING BIT THROW- AWAY MEMORY Richard H. Tuhro

Proposed Classification U.S. Cl. 358/280 Int. Cl. H04n 1/40

To implement image reduction in electronic imaging systems, a pixel throw-away is ordinarily used. Large Scale Integrated (LSI) circuits work well for this applicationwithin certain limits. Two difficulties which exist, however, are that the Transistor Transistor Logic (TTL) Binary Rate Multipliers (BRMs) presently available will not work at high data rates (i.e., 25 MHz is a typical maximum) and some applications require that not only the number of pixels to be deleted be known but also require that the pixels to be deleted be identified.         While         the         BRM approach behaves precisely, it is difficult to calculate before hand exactly which pixels are to be deleted.

Referring to the figure, an alternate approach stores the pixel delete (or save) pattern in memory 6. Semiconductor memories are fast, inexpensive and offer an easy to understand approach which eliminates the problems mentioned above. Memory 6 is addressed by a counter 7. Counter 7 is driven by the system pixel clock through divide-by-8 counter 9 so that a change occurs every 8 pixels, thus providing a modest memory rate; i.e., a 40 MHz pixel rate becomes a 5 MHz (200Ns) memory rate. The output of memory 6 is fed to parallel-to-serial buffer 10 controlling the enabling of pixel clock gate 11 and, in turn, pixel throw-away.