Browse Prior Art Database

ASYNCHRONOUS CHARGE-COUPLED DEVICE IMAGER (CCD) ARCHITECTURE

IP.com Disclosure Number: IPCOM000024716D
Original Publication Date: 1981-Oct-31
Included in the Prior Art Database: 2004-Apr-02
Document File: 4 page(s) / 143K

Publishing Venue

Xerox Disclosure Journal

Abstract

The conventional architecture of a Charge-Coupled Device (CCD) imaging chip 5 of the type used with raster image scanning systems is shown in Figure 1. The CCD 5 normally integrates the irradiance on the photosites 6 during the integration time, then transfers the generated electrons to an on board shift register 7. During the next integration period, the CCD shift register 7 shifts out the serial data while the photosites 6 are accumulating a new charge. To operate the CCD's at the maximum allowable speed, the integration time is made equal to the time required to empty the shift register 7. This allows the photosites 6 to integrate for the maximum allowable time, taking advantage of all the possible irradiance. This scheme also allows the CCD shift register 7 to shift out over as long a period as possible, providing minimum data rate for the integration time used. These capabilities are important where the CCD is scanning objects at high speed. It also means, however, that the CCD must be operated in a synchronous fashion, i.e., for a constant integration time, the shift register must be clocked at a constant rate.

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Page 1 of 4

XEROX DISCLOSURE JOURNAL

ASYNCHRONOUS CHARGE-COUPLED DEVICE IMAGER (CCD) ARCHITECTURE Ronald G. Matteson

Proposed Classification
U.S. C1. 358/213 Int. Cl. H04n 3/14

.6 FIG /

Volume 6 Number 5 September/October 1981

DATA

FIG 3

DUMP

DATA

277

[This page contains 1 picture or other non-text object]

Page 2 of 4

ASYNCHRONOUS CHARGE-COUPLED DEVICE IMAGER (CCD) ARCHITECTURE

(Lont'dl

FIG 2

INTEGRATION COMMAND

PERIOD INTEGRATION SCAN LINE ISCAN 2 1 21 I I I

CHARGE TRANSFER

N Rl I

        / /r DATA DESTROYED BY INTEGRATION COMMAND AND CHARGE DUMP

DATA

INTEGRATION COMMAND

 INTEGRATION PERIOD CHARGE TRANSFER To

  REGISTER 9 CHARGE TRANSFER TO

FIG 4

nn nn n

m

7 REGISTER SCAN LINE I SCANLINE 2

DATA L I It

278

    XEROX DISCLOSURE JOURNAL Volume 6 Number 5 September/October 1981

[This page contains 1 picture or other non-text object]

Page 3 of 4

ASYNCHRONOUS CHARGE-COUPLED DEVICE IMAGER (CCD) ARCHITECTURE (Cont'd)

The conventional architecture of a Charge-Coupled Device (CCD) imaging chip 5 of the type used with raster image scanning systems is shown in Figure 1. The CCD 5 normally integrates the irradiance on the photosites 6 during the integration time, then transfers the generated electrons to an on board shift register 7. During the next integration period, the CCD shift register 7 shifts out the serial data while the photosites 6 are accumulating a new charge. To operate the CCD's at the maximum allowable speed, the integration time is made equal to the time required to empty the shift register 7. This allows the photosites 6 to integrate for the maximum allowable time, taking advantage of all the possible irradiance. This scheme also allows the CCD shift register 7 to shift out over as long a period as possible, providing minimum data rate for the integration time used. These capabilities are important where the CCD is scanning objects at high speed. It also means, however, that the CCD must be operated in a synchronous fashion, i.e., for a constant integration time, the shift register must be clocked at a constant rate.

It is advantageous to the design of some scanning systems to operate the CCD 5 asynchronously, i.e., to provide scan lines clocked out at a constant bit rate, but at a scan line rate of anything up to the maximum achieved during synchronous operation. The problems in trying to do this with conventional CCDI architecture are shown in Figure 2. At a speed slightly slower than maximum, integration can be started on command and end after the fixed integration period. Data can be transferred to the shift register and shifting out of...