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Browse Prior Art Database

PHOTOLITHOGRAPHIC PROCESS FOR FABRICATING THIN FILM TRANSISTORS

IP.com Disclosure Number: IPCOM000025077D
Original Publication Date: 1983-Jun-30
Included in the Prior Art Database: 2004-Apr-04
Document File: 2 page(s) / 147K

Publishing Venue

Xerox Disclosure Journal

Abstract

This proposal provides a process which takes advantage of the single vacuum pump-down technique for minimizing contamination of the critical thin film transistor interfaces. This single pump-down technique is incorporated into an all photo-lithographic process, thus realizing the high degree of control and resolution afforded thereby. During the one pump-down step, the critical and contamination vulnerable semiconductor-insulator interfaces are formed by sequential deposition of a transistor gate insulator layer, a semiconductor pad, and top insulator layer. The top insulator serves as a passivating layer on the free surface of the single gated thin film transistor, or as a top gate insulator in a double gated thin film transistor. I

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[EROX DISCLOSURE JOURNAL

PHOTOLITHOGRAPHIC PROCESS FOR Proposed Classification FABRICATING THIN FILM TRANSISTORS
U.S. Michael Poleshuk Cl. 427/89
Int. Cl. R05d 5/12

25

I2

This proposal provides a process which takes advantage of the single vacuum pump- down technique for minimizing contamination of the critical thin film transistor interfaces. This single pump-down technique is incorporated into an all photo- lithographic process, thus realizing the high degree of control and resolution afforded thereby. During the one pump-down step, the critical and contamination vulnerable semiconductor-insulator interfaces are formed by sequential deposition of a transistor gate insulator layer, a semiconductor pad, and top insulator layer. The top insulator serves as a passivating layer on the free surface of the single gated thin film transistor, or as a top gate insulator in a double gated thin film transistor. I

In addition to the one pump-down formation of critical semiconductor-insulator interfaces and encapsulation of contamination vulnerable thin film transistor surfaces prior to wet processing, the present technique provides one pump-down provision of a passivating layer for the free surface of single gated devices and one pump-down formation of both gate insulator for double gated devices. As well, to minimize set coverage problems, a quasi-planar construction is employed. Thus, to eliminate the need for continuous coverage of the vertical source-drain electrode walls, a planar substructure for the thin semiconductor layer is provided. To further minimize contamination, dry plasma etching is employed to expose the source-drain contact areas on the semiconductor pad.

Volume 8 Number 3 May/June 1983 287

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PHOTOLITHOGRAPHIC PROCESS FOR FABRICATING THIN FILM TRANSISTORS (Cont'd)

In accordance with one particularly advantageous embodiment as shown in the figure, the fabrication sequence utilizes nickel, aluminum oxide, cadmium selenide, semiconductor, top insulator, and source and drain contacts, respectively. This sequence is initiated by the formation of a nickel gate electrode 12 on a portion of a surface of an aluminum oxide insulating coating 11 on substrate 10 by, for example, subtractive photolithographic delineation. Without removing the photo- resist masks (not shown) employed to delineate the nickel gate electrode 12, a planar structure is formed by depositing aluminum oxide 15 over the insulating coated substrate 11 to a thickness substantially equal to the thickness of the gate electrode. A gate insulator layer 16 is then formed on top of the planar surface formed by gate electrode 12 and insulator layer 15. Thereafter, nickel sourc...