Browse Prior Art Database

METHOD OF FORMING A HIGH DENSITY ELECTRICAL CIRCUIT AND INTERCONNECTS THERETO

IP.com Disclosure Number: IPCOM000025080D
Original Publication Date: 1983-Aug-31
Included in the Prior Art Database: 2004-Apr-04
Document File: 4 page(s) / 164K

Publishing Venue

Xerox Disclosure Journal

Abstract

The electrical connection of one point in an electronic device to some other point is accomplished by a variety of means and over a wide range of densities. In the microelectronics art, these electrical interconnect methods include a point-to-wiring, conventional (and increasingly unconventional) printed circuit boards, thick and thin film hybrid circuits, redundant and non-redundant elastomeric conductors, and mask defined metallization patterns executed at chip level. With the increasing complexity of integrated circuits and other electronic devices, there has arisen a need to provide interconnecting conductor patterns with increasingly high densities. Meeting this objective exceeds or strains the capabilities of the foregoing technologies. Efforts to provide truly high resolution, or fine line geometries, also necessarily raise concomitant problems of providing commercially feasible means of electrically interconnecting the dense conductors to other system components as, for example, to associated driver circuits.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 4

XEROX DISCLOSURE JOURNAL

METHOD OF FORMING A HIGH

Richard Kellerman Gary A. Kneezel

Proposed Classification
U.S. Cl. 29/625 Int. C1. H05k 3/12

The electrical connection of one point in an electronic device to some other point is accomplished by a variety of means and over a wide range of densities. In the microelectronics art, these electrical interconnect methods include a point-to- wiring, conventional (and increasingly unconventional) printed circuit boards, thick and thin film hybrid circuits, redundant and non-redundant elastomeric conductors, and mask defined metallization patterns executed at chip level. With the increasing complexity of integrated circuits and other electronic devices, there has arisen a need to provide interconnecting conductor patterns with increasingly high densities. Meeting this objective exceeds or strains the capabilities of the foregoing technologies. Efforts to provide truly high resolution, or fine line geometries, also necessarily raise concomitant problems of providing commercially feasible means of electrically interconnecting the dense conductors to other system components as, for example, to associated driver circuits.

Volume 8 Number 4 July/August 1983 293

[This page contains 1 picture or other non-text object]

Page 2 of 4

METHOD OF FORMING A HIGH DENSITY ELECTRICAL CIRCUIT AND INTER- CONNECTS THERETO (Cont'd)

In accordance with the present proposal and as shown in the accompanving figure, a preferred method and alternatives for forming high density conductive circuit patterns and electrical interconnections thereto are presented. The intercon- nections are spaced in two dimensional (area) arrays to provide bonding points compatible with existing interconnection technologies.

To initiate the process, a thin film layer of photosensitive material 14 having a uniform thickness is formed on a smooth surface 12 of a conductive substrate 10. The photosensitive material is then photolithographically processed in pattern-wise fashion to expose selected portions of the smooth surface of the substrate. The expose portions of the substrate are then electroplated to form the desired conductive circuit pattern such as elongate bus bars having mushroom cross sectional shapes as shown at 18a and 18b. This circuit pattern is then covered with a layer of insulating material 11. Thereafter, vias, for example, 13a and 13h, are formed through the layer of insulating material to expose the underlying con- ductive circuit pattern (bus bars). The vias are spaced one from another in a predetermined two dimensional array and, generally, only one to a bus bar, so that the spacing between adjacent vias 13a, 13h is greated then the spacing of adjacent conductors 18a, 18b in the underlying circuit. Next, the layered substrate is immersed in a plating bath where raised mushroom-shaped bump interconnects 15 to the conductive circuit or bus bars are formed by electroplating through each via and over the insulating layer t...