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IMPLEMENTATION TECHNIQUE FOR MAGNIFICATION, REDUCTION, AND WINDOWING OF ELECTRONIC IMAGES

IP.com Disclosure Number: IPCOM000025230D
Original Publication Date: 1984-Feb-29
Included in the Prior Art Database: 2004-Apr-04
Document File: 4 page(s) / 151K

Publishing Venue

Xerox Disclosure Journal

Abstract

Image Input Terminal (IIT) designs may incorporate algorithms for reduction, magnification, and windowing. In some cases, bit rate multipliers may be used, in others, Random Access Memory (RAM) storage devices which store a precomputed pattern for reduction and/or windowing. Special counters may also be used to generate the bit patterns required for magnification and reduction.

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XEROX DISCLOSURE JOURNAL

IMPLEMENTATION TECHNIQUE FOR MAGNIFICATION. REDUCTION. AND

FACE

Proposed Classification
U.S. Cl. 358/287 Int. Cl. H04n 1/04

WINDOWING OF ELECTRONIC IMAGES Ronald G. Matteson

FIG I

2X DATA CLOCK

LINE SYNC.

RESET

X ADDR

X RAM

16KxI

RESET Y ADDR

I

I I

14

MPU

. .?AM 16K x I

lo

- - 1 :, -+J-

Volume 9 Number 1 January/February 1984 73

8-BIT

+ P/S

[This page contains 1 picture or other non-text object]

Page 2 of 4

IMPLEMENTATION TECHNIQUE FOR MAGNIFICATION, REDUCTION, AND WIN- DOWING OF ELECTRONIC IMAGES (Cont'd)

2-EIT

A/ D

LINE SYNC.

 LD / R EClRC . f- /RECIRC. DATA

'BIT2

IX CLOCK

.4

 M PU INTER- FACE

MPU

4 x,2

4-LEVE L

B

f

-I

2- BIT

A'

5

    XEROX DISCLOSURE JOURNAL Volume 9 Number 1 January/February 1984

74

[This page contains 1 picture or other non-text object]

Page 3 of 4

IMPLEMENTATION TECHNIQUE FOR MAGNIFICATION, REDUCTION, AND WIN- DOWING OF ELECTRONIC IMAGES (Cont'd)

Image Input Terminal (IIT) designs may incorporate algorithms for reduction, magnification, and windowing. In some cases, bit rate multipliers may be used, in others, Random Access Memory (RAM) storage devices which store a precomputed pattern for reduction and/or windowing. Special counters may also be used to generate the bit patterns required for magnification and reduction.

Figure 1 of the drawings shows a system using RAM memories 5, 6 for storing patterns for magnification/reduction and windowing in both x and y directions. The patterns stored in RAMS 5, 6 are computed by any suitable algorithm resident in the IIT MPU 4. The outputs of RAMS 5, 6 are applied to gates 7, 8 respectively, which enable or inhibit the data clock and line sync pulses of the 117'.

In a simplification of the approach, the y-RAM and y-address counters 9, 10 may be omitted. In that case, for reduction, the y data can be stored in the RAM associated with MPU 4 and supplied directly from the parallel-to-serial converter 11 to gate 12, the latter to inhibit or enable the IIT line sync control signals. For magnification, the microstepping control logic for the IIT stepper-motor drive can be programmed to take smaller steps, i.e., scan more slowly.

I

As an alternate to RAM storage, analog storage devices such as Charge Coupled Devices (CCD) may be used. Referring to Figure 2, a magnification, reduction, and windowing scheme using...