Browse Prior Art Database

POLYCELL PLACE AND ROUTE TECHNIQUE

IP.com Disclosure Number: IPCOM000025233D
Original Publication Date: 1984-Feb-29
Included in the Prior Art Database: 2004-Apr-04
Document File: 2 page(s) / 52K

Publishing Venue

Xerox Disclosure Journal

Abstract

It is well known in hand routing of chip design layouts to incorporate buffer drivers in long lines. The present invention relates to an improved polycell chip design technique for automatically placing. logic elements (cells) and optimally routing their interconnects (lines). The placement of cells is accomplished by a computer having a library of generic logic functions and being given specific logic in-structions for a given chip design. It is the intention of this invention that the place and route program optimize and equalize the intercell signal transit times, i.e. there should be no intercell signal propagation time longer than any other, since the chip can only operate as fast as the slowest transit time.

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XEROX DISCLOSURE JOURNAL

~ ~~ POLYCELL PLACE AND ROUTE TECHNIQUE
Donald Schar f e tter

Volume 9 Number 1 January/February 1984 83

Proposed Classification
U.S. C1. 364/154 Int. Cl. G05b 13/02

It is well known in hand routing of chip design layouts to incorporate buffer drivers in long lines. The present invention relates to an improved polycell chip design technique for automatically placing. logic elements (cells) and optimally routing their interconnects (lines). The placement of cells is accomplished by a computer having a library of generic logic functions and being given specific logic in- structions for a given chip design. It is the intention of this invention that the place and route program optimize and equalize the intercell signal transit times,
i.e. there should be no intercell signal propagation time longer than any other, since the chip can only operate as fast as the slowest transit time.

In order to achieve the results of the invention, each cell is provided in two parts, first a logic function and second an expandable buffer driver. In placing each cell, the computer attempts to optimize its location to minimize long cell inter- connects. However, when it is inevitable that a long interconnect must be utilized, the computer will increase the size of the buffer driver, thus increasing the buffer driver &rent and reducing delay time.

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    XEROX DISCLOSURE JOURNAL Volume 9 Number 1 Ja...