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SENSORS AND SENSOR CHIPS FOR FULL WIDTH ARRAYS

IP.com Disclosure Number: IPCOM000025700D
Original Publication Date: 1987-Jun-30
Included in the Prior Art Database: 2004-Apr-04
Document File: 4 page(s) / 140K

Publishing Venue

Xerox Disclosure Journal

Abstract

The idea of making a full width array (11" - 17") from shorter (0.2" - 1") sensor array chips has been around for a few years. The actual implementation of such an idea requires design and fabrication of suitable short array chips, development and realization of practical assembly methods, and connection and addressing of the full width array.

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XEROX DISCLOSURE JOURNAL

SENSORS AND SENSOR CHIPS FOR FULL WIDTH ARRAYS Mehdi N. Araghi

Proposed Classification

U.S. C1. 156/645 Int. C1. B44c 1/22

7

Volume 12 Number 3 May/June 1987 123

[This page contains 1 picture or other non-text object]

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SENSORS AND SENSOR CHIPS FOR FULL WIDTH ARRAYS (Cont'd)

The idea of making a full width array (11" - 17") from shorter (0.2" - 1") sensor array chips has been around for a few years. The actual implementation of such an idea requires design and fabrication of suitable short array chips, development and realization of practical assembly methods, and connection and addressing of the full width array.

In assembling a multi-segmented full width array, several important factors have to be considered. Three of these are addressed here, namely, deviation of scan line from linearity (geometrical straightness of sensor line), end to end ixel spacing effects (stitching between short arrays), and pixel dropout at

r2 utted ends.

In order to have a uniform and straight line of scan, the shape of the active area of the array sensors 5 must be designed properly. Referring to Figure 1, it is suggested that the active area extend several pixel sizes in the cross scan direction. For example, at a pixel spacing of 50 microns (center-to-center), the active size of each sensor 5 may be chosen to be 40 microns along the scan direction and 300 microns across the scan. After the short array chips 6 are abutted and reasonably coarsely aligned (with respect to a reference line), an opaque shadow mask 7 can be formed on to of the full width array 4 by

pixel width (e.g. 50 pm). Window 8, by virtue of this technique, is very straight and uniform. Present tolerances available in manufacturing substrates with alignment marks, reference edges, etc. point to a 7:l aspect ratio in the design of the sensors 5 (@ 500 lpi resolution). In general, there may be a speed penalty in operation of such a large area sensor, mainly due to increased sensor capacitance. This difficulty ma be overcome by using

masked portion of the sensor by proper application of a voltage to the mask, which is a metalization overlay.

photolithographic techniques such that the c P ear window 8 is of the proper

proper circuit designs at the chip level. Also, it may

E e possible...