Browse Prior Art Database

FAST NMOS ADDER

IP.com Disclosure Number: IPCOM000025872D
Original Publication Date: 1988-Aug-31
Included in the Prior Art Database: 2004-Apr-04
Document File: 6 page(s) / 250K

Publishing Venue

Xerox Disclosure Journal

Abstract

A fast carry-look-ahead adder useful for new VLSI designs. A 16-bit version of this adder has been implemented which calculates a sum in less than 50 nanoseconds (including pad delays). Simulations of a 37-bit adder with stronger pullups indicate the even faster add times that can be achieved.

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Page 1 of 6

EROX DISCLOSURE JOURNAL

FAST NMOS ADDER

Proposed Sidney W. Marshall Classification

US. C1.36011 Int. C1. Gllb 5/00

FIG. IA (Adder)

7

FIG. 16

(000 LEVEL LOOK AHEAD)

I

i

I, '1

FIG. 1C

(EVEN LEVEL LOOKAHEAD)

Volume 13 Number 4 July/August 1988 229

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Page 2 of 6

FAST NMOS ADDER (Cont'd)

FIG. 2

  XEROX DISCLOSURE JOURNAL Volume 13 Number 4 July/August 1988

230

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Page 3 of 6

FAST NMOS ADDER (Cont'd)

ICI FIG. 3

XEROX DISCLOSURE JOURNAL

Volume 13 Number 4 July/August 1988 23 1

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Page 4 of 6

FAST NMOS ADDER (Cont'd)

A fast carry-look-ahead adder useful for new VLSI designs. A 16-bit version of this adder has been implemented which calculates a sum in less than 50 nanoseconds (including pad delays). Simulations of a 37-bit adder with stronger pullups indicate the even faster add times that can be achieved.

The generation of the carry is the most time-consuming operation in an adder. Once the carry is known for each bit the sum can be calculated quickly by a simple combinatorial circuit. Ripple-carry adders generate the carryout from each stage from the carry in to the same stage. Each stage supplies the carry for the next stage. The worst case add time results when a carry must ripple for propagate through the entire length of the adder. The worst case addition time is therefore proportional to the number of bits in the adder.

Look-ahead adders generate the carries in a more parallel fashion. The trick is to propagate the carry across several bits in a single logic operation. This is done by generating auxiliary functions "P" (for propagate) and "G" (for generate). These signals are associated with blocks of bits in the adder. P means that this block will produce a carry if there is a carry into the block. G means that a carry is produced by this block regardless of any carry into the block. If G true then a carry is produced and the value of P is irrelevant.

The generation of the P and G signals for a block consisting of single bit of the adder is easy. If the inputs to the bit are A and B then

P=A+B

G = AB

The equations for the sum S in each bit cell of the adder (in terms of a carry C
that must be generated) is:

If there are two adjacent blocks each producing their own P and G signals then the P and G signals for the combined block are given by

P = POP1

July/August 4 Number 13 Volume XEROX 232 DISCLOSURE JOURNAL 1988

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FAST NMOS ADDER (Cont'd) .

(3)

G = G1+ PlGO

We must also generate the carry in to each bit of the adder. The carry in for the least significant bit of the adder is the same as the carry in for the block. The carry in for the most significant block of a merged pair of blocks is:

CO = C leastsignificantcarry

(4) C1 = GO + POC most significant carry

We now have an inductive method for constructing adders...