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CHANNEL PLATE FABRICATION IN AN INK JET PRINTER

IP.com Disclosure Number: IPCOM000025921D
Original Publication Date: 1989-Feb-28
Included in the Prior Art Database: 2004-Apr-04
Document File: 2 page(s) / 67K

Publishing Venue

Xerox Disclosure Journal

Abstract

Ink jet printer design incorporates an architecture which includes a silicon based channel and heater plate. The heater plate contains active circuit components (MOS drivers and, optionally, logic) while the channel plate's thermal expansion coefficient is matched to that of the heater plate. In fabricating circuit chips containing the circuit components, it is necessary to isolate adjacent discrete devices. One method used is to form vertical branches between these discrete devices by a reactive ion etching process. The trench usually is very narrow ($1-2p) and deep ($10 to 20p). The wafer is subsequently planarized by deposition of a conformal Si02 film (such as TEOS-CVD) (tetra-ethyl-ortho silicate), which fills the trenches when deposited to about half of the trench width. The same equipment which is used to form vertical wall trenches can be used to form the channels and nozzle structure. For example; a two-step ODE-RIE process, where ODE (Orientation Dependent Etching) is used to form through-wafer fill holes using a CVD Si3N4 mask followed by strip of the Si3N4 mask, exposing an underlying Si02 mask which can then be used to mask RIE of the channels. A three-step process is also possible where the second step includes pre-RE etch of the face of the channel plate, followed by etch of the channels and a deeper etch of the nozzle face area.If a complete through wafer RIE etch is not feasible, a very smooth finish of the area immediately surrounding the nozzles may still be provided.

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XEROX DISCLOSURE JOURNAL

CHANNEL PLATE FABRICATION Proposed Classification IN AN INK JET PRINTER
William G. Hawkins
Donald J. Drake

U.S. C1.346/140 Int. C1. Gold 15/16

Ink jet printer design incorporates an architecture which includes a silicon based channel and heater plate. The heater plate contains active circuit components (MOS drivers and, optionally, logic) while the channel plate's thermal expansion coefficient is matched to that of the heater plate. In fabricating circuit chips containing the circuit components, it is necessary to isolate adjacent discrete devices. One method used is to form vertical branches between these discrete devices by a reactive ion etching process. The trench usually is very narrow ($1-2p) and deep ($10 to 20p). The wafer is subsequently planarized by deposition of a conformal Si02 film (such as TEOS-CVD) (tetra-ethyl-ortho silicate), which fills the trenches when deposited to about half of the trench width. The same equipment which is used to form vertical wall trenches can be used to form the channels and nozzle structure. For example; a two-step ODE-RIE process, where ODE (Orientation Dependent Etching) is used to form through-wafer fill holes using a CVD Si3N4 mask followed by strip of the Si3N4 mask, exposing an underlying Si02 mask which can then be used to mask RIE of the channels. A three-step process is also possible where the second step includes pre-RE etch of the face of the channel plate, followed by etch of the chan...