Browse Prior Art Database

HARDWARE FAULT ISOLATION STRATEGY

IP.com Disclosure Number: IPCOM000026217D
Original Publication Date: 1990-Oct-31
Included in the Prior Art Database: 2004-Apr-05
Document File: 2 page(s) / 74K

Publishing Venue

Xerox Disclosure Journal

Abstract

In a machine control system having a plurality of processors and a plurality of buses with a single memory board, it is difficult to isolate hardware failures within the control system. The strategy depicted in the above figure facilitates the isolation of hardware faults in multiprocessor/multi-bus systems to a printed wiring board (PWB) level, wherein it is assumed that each PWB has a microprocessor (pP) which has access to system memory. In general, the strategy applies a two tier test to isolate the hardware faults. Referring to the figure, the strategy begins by running a complete systems diagnostic test, wherein each PWB containing a microprocessor executes a test to determine if access to system memory is successful, block 12. If more than one pP fails this test, as determined at block 14, the fault is isolated to the system memory board, block 16. If only one pP fails, the failed microprocessor is deactivated, block 18, and the diagnostic test is rerun on the remaining pP's at block 20. Should any of the remaining pP's fail the test, the system memory board would be indicated as having the fault. If, however, the remaining pP's pass the tests, the deactivated pP is indicated as having the fault.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 84% of the total text.

Page 1 of 2

XEROX DISCLOSURE JOURNAL

     RUN Dl AG N OSTl CS TEST

DEACTIVATE

IFAILED pP PWB

    RE-RUN DIAGNOSTICS TEST

HARDWARE FAULT ISOLATION Proposed Classification STRATEGY U.S. C1.355/164 Gregory C. Crawford
C1. Int. Mark A. Smith G05b 13/02

12

/

18

20 /--

I DEACTIVATED I

MEMORY PWB

XEROX DISCLOSURE JOURNAL Vol. 15 No. 5 September/October 1990 385

[This page contains 1 picture or other non-text object]

Page 2 of 2

HARD WARE FAULT ISOLATION STRATE GY(Cont'd)

In a machine control system having a plurality of processors and a plurality of buses with a single memory board, it is difficult to isolate hardware failures within the control system. The strategy depicted in the above figure facilitates the isolation of hardware faults in multiprocessor/multi-bus systems to a printed wiring board (PWB) level, wherein it is assumed that each PWB has a microprocessor (pP) which has access to system memory. In general, the strategy applies a two tier test to isolate the hardware faults. Referring to the figure, the strategy begins by running a complete systems diagnostic test, wherein each PWB containing a microprocessor executes a test to determine if access to system memory is successful, block 12. If more than one pP fails this test, as determined at block 14, the fault is isolated to the system memory board, block 16. If only one pP fails, the failed microprocessor is deactivated, block 18, and the diagnostic test is rerun on the remaining pP's at block 20. Should any of the remaining p...