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n+ DOPANT MODULATION OF BORON'S DIFFUSION COEFFICIENT FOR SELF-ALIGNED p+ SUBSTRATE CONTACTS

IP.com Disclosure Number: IPCOM000026511D
Original Publication Date: 1992-Jun-30
Included in the Prior Art Database: 2004-Apr-06
Document File: 4 page(s) / 173K

Publishing Venue

Xerox Disclosure Journal

Abstract

A modified NMOS fabrication technique is disclosed which produces self-aligned substrate contacts on smart power NMOS logic and driver chips. Standard fabrication techniques do not have provisions to generate ohmic contacts on the surface of the substrate. Typically the ohmic contact is generated on the back side of the substrate by a lapping (grinding) and gold alloying process.

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XEROX DISCLOSURE JOURNAL

n+ DOPANT MODULATION OF BORON'S DIFFUSION U.S. C1.437/142 COEFFICIENT FOR SELF-ALIGNED
p+ SUBSTRATE CONTACTS
William G. Hawkins

Proposed Classification Int. C1. HOlr 21/22

Transistor Region Contact Region

-______-------

POlY

 - Field Oxide ________------- I

I I

I {

I

20 - -2 ___-_------ ---- - - -1.

_____------

__---- --------____-

L-----______---

NG. 1

XEROX DISCLOSURE JOURNAL - Vol. 17, No. 3 May/June 1992 193

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n+ DOPANT MODULATION OF BORON'S DIFFUSION COEFFICIENT CONTACTS( Cont'd) FOR SELF-ALIGNED p+ SUBSTRATE

A modified NMOS fabrication technique is disclosed which produces self- aligned substrate contacts on smart power NMOS logic and driver chips. Standard fabrication techniques do not have provisions to generate ohmic contacts on the surface of the substrate. Typically the ohmic contact is generated on the back side of the substrate by a lapping (grinding) and gold alloying process.

Back side contacts along with their fabrication techniques have several negative characteristics for applications such as thermal ink jet (TIJ): thickness tolerance is lost when lapping occurs for wafers requiring thickness variations within f2 or 3 micro meter. The thickness control allows the distance from the back of a wafer to the jets to be precisely aligned. The gold on the backside causes the wafer to become opaque when infrared (IR) through-wafer alignment is used to place the channel plate over the heater plate of the TIJ, both of which are transparent in the IR. The lapping process destroys the surface finish of the back of the wafer causing the IR light to scatter. Because power MOS (high voltage) devices integrated with logic circuitry generate substantial substrate currents induced by their high fields, resistances between the front and back side of the wafer can cause a substantial bias to develop on the front side of the wafer. The induced bias can be detrimental to logic functions through threshold shift and may result in parasitic bipolar action in the driver section of the TIJ.

One possible process flow for power MOS transistors with self-aligned substrate contacts is shown in Figure 1. The figure is divided into two regions, the transistor region and the substrate contact region. First, substrate regions 10 and 20 are doped to form n- regions. Subsequently in the transistor region 30, an n+ contact is formed offset from the gate by an n- drift region, while the substrate contact region 40 is masked from the n+ implant. Following reoxidation, glass deposition and flow, via cuts are made in both regions.

A boron implant dose is adjusted so that the energy of the entire implant is...