Browse Prior Art Database

A HIGH SPEED COMPARATOR

IP.com Disclosure Number: IPCOM000026637D
Original Publication Date: 1993-Feb-28
Included in the Prior Art Database: 2004-Apr-06
Document File: 6 page(s) / 164K

Publishing Venue

Xerox Disclosure Journal

Abstract

Comparator circuits are used very commonly in analog-to-digital and digital-to-analog converters. Recently, there has been an increasing trend towards the use of CMOS technology because of the low power consumption and good analog performance of these circuits.

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Page 1 of 6

XEROX DISCLOSURE JOURNAL

A HIGH SPEED COMPARATOR Jagdish C. Tandon
David
J. Metcalfe

Proposed Classification

US. C1.330/001R Int. C1. H03F 1/00, H03F 21/00

4

TRANSMISSION FIG. I(a) GATE

"Out

4 3 INVERTER Vout vs. Vin 2 !-I w

FIG. l(b)

XEROX DISCLOSURE JOURNAL - Vol. 18, No. 1 January/February 1993 17

[This page contains 1 picture or other non-text object]

Page 2 of 6

A HIGH SPEED COMPARATOR(Cont'd)

PCHN S.F. NCHN S.F.

PCHN S.F. NCHN S.F.

Vout

6

FIG. 2(a)

Vin vs. Vout

Vout

5l

t

4

7 TOGGLEPOINT

-

1 \TOGGLE ZONE

IIIIIIIIII

b

FIG. 2(b)

18 XEROX DISCLOSURE JOURNAL - Vol. 18, So. 1 JanuaryIFebruary 1993

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Page 3 of 6

A HIGH SPEED COMPARATOR(Cont'd)

I\t

5 5 1 1

             A21 A22 A23 cLKA ANALOG COMPARE

NODE CLKC

CIRCUITRY

DECODE CIRCUITRY 83 82 B1 BO

I I I I I I I I

                   I I I 1 I I I I

j ~22 i I I I I I

I

I I I

I I

I I 1 I I I

FIG. 3(a)

i\ i i

i CLKA i / I 1 I I I I

I

U I I I 1-

I I I I I I

I I

i CLKB i

I I I I I I

i CLKC i I I I I

FIG. 3(6) I I I I I I I

XEROX DISCLOSURE JOURNAL - Vol. 18, Xo. 1 January/February 1993 19

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Page 4 of 6

A HIGH SPEED COMPARATOR(Cont'd)

Comparator circuits are used very commonly in analog-to-digital and digital- to-analog converters. Recently, there has been an increasing trend towards the use of CMOS technology because of the low power consumption and good analog performance of these circuits.

An example of a t ical CMOS comparator circuit'is shown in Figure la.

coupling capacitor 4 are used to form one comparator stage. While a series of these comparator stages can be cascaded to form a high-gain comparator circuit, the overall speed of the high-gain comparator circuit of the type shown is limited by the speed of the individual comparator stages.

There, a basic CMO 3 inverter circuit 2 along with a transmission gate 3 and

The present proposal provides a high speed comparator circuit 5 by the inclusion of a double source follower stage 6 at the output of the inverter as shown in Figure 2a. A high-gain comparator circuit 8 using plural speed- enhanced comparator circuits 5 cascaded together is shown in Figure 3a. As can be seen, the proposed high-gain comparator circuit 8 consists of a source follower buffer stage 9, two high speed comparators circuits 5, one inverter- comparator 10, and latch circuit 12. In use, buffer 9 helps to lower the input capacitance and reduces the clock feed through voltage, generated via the comparator's transmission gates TG1 and TG2, from propagating into the analog portion of the A/D converter.

At the start of t...