Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

ROM MEMORY MANAGER

IP.com Disclosure Number: IPCOM000026665D
Original Publication Date: 1993-Feb-28
Included in the Prior Art Database: 2004-Apr-06
Document File: 2 page(s) / 94K

Publishing Venue

Xerox Disclosure Journal

Abstract

Machine control software is often stored in read only memories (ROMs) which are plugged into sockets on a circuit board. Because the software code sometimes changes after product introduction, it is often necessary to change these ROMs in the field. Since there are often several ROMs on a circuit board, it becomes a problem to get the ROM containing the correct revision and code sequence plugged into the correct socket. While this problem can be solved by using color or mechanically coded ROMs, this adds additional unwanted processing and handling costs.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 64% of the total text.

Page 1 of 2

XEROX DISCLOSURE JOURNAL

ROM MEMORY MANAGER Classification Proposed Richard H. Tuhro US. C1.365/103

Int. C1. Gllc 17/00

8 3 \ 3 \

r-

XEROX DISCLOSURE JOURNAL - Vol. 18, No. 1 JanuaryiFebruary 1993 97

[This page contains 1 picture or other non-text object]

Page 2 of 2

ROM MEMORY MANAGE R(Cont'd)

Machine control software is often stored in read only memories (ROMs) which are plugged into sockets on a circuit board. Because the software code sometimes changes after product introduction, it is often necessary to change these ROMs in the field. Since there are often several ROMs on a circuit board, it becomes a problem to get the ROM containing the correct revision and code sequence plugged into the correct socket. While this problem can be solved by using color or mechanically coded ROMs, this adds additional unwanted processing and handling costs.

In the present disclosure and referring to the drawing Figure, the various ROMs 3 intended for field update have a few memory locations reserved for ROM identification. This identification could consist of an intended code sequence identifier, version identifier, parity check, etc. Each ROM 3 would include the appropriate sequence, version, and check identification.

A processor unit 5 with fixed code memory 6 executes software code at an appropriate time (i.e., at power up or on restart) that sets up a memory controller 8 to a specific predetermined arrangement so that the changeable identification of each ROM 3 may be int...