Browse Prior Art Database

APPARATUS FOR DEBOUNCING SIGNALS

IP.com Disclosure Number: IPCOM000026819D
Original Publication Date: 1993-Oct-31
Included in the Prior Art Database: 2004-Apr-06
Document File: 8 page(s) / 411K

Publishing Venue

Xerox Disclosure Journal

Abstract

Debounce and lockout filters for simultaneously processing multiple noisy signals to produce multiple corresponding debounced signals are disclosed. More specifically in Figure 1, filter 20 includes input part 22, processor 24, output part 26 and memory 28. Inputs to the filter processor are a plurality of voltage signals Vl-VN. Outputs from filter 20 include filtered signals Fl-FN. Inputs V1-VN are produced by switch circuits 10. Input voltages V1-VN are provided to corresponding gates GI-GN. Sampling signal TM is provided to each of the gates GI-GN to produce binary signals B1,M-BN7M. Signals B1,%- BN,M constitute a plurality of binary signals having a sequence of values indexed on index designator M. A current value from each of the plurality of binary signals is provided to register 32 where the plurality of current values are retained until read in by processor 24. Preferably input part 22 is part of a microprocessor comprised of input part 22, processor 24 and output part 26. A multiplexer may be advantageously interposed between switch circuits 10 and input part 22 to select between multiple sets of switch voltage V. The value of each signal at a point in time is either in an ON state or an OFF state (logical "1" or logical "0"). Figure 2 shows a filter input signal changing states several times before finally remaining in one state. Figure 2 also shows a debounced filter output signal switching to its output state after the debounce filter time.

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Page 1 of 8

XEROX DISCLOSURE JOURNAL

APPARATUS FOR DEBOUNCING Proposed Classification SIGNALS U.S. C1.3641943.9 Michael K. Hawes Int. C1. G06f OO/OO

32 \- REGISTERS

-I

TM

22

4

24 PROCESSOR MEMORY

XEROX DISCLOSURE JOURNAL - Vo1.18,No. 5 SepternbedOctober 1993 545

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Page 2 of 8

APPARATUS FOR DEBOUNCING SIGNALS(Cont'd)

Filter Input Signal Filter OutDut Sianal

   FIG. 2 Filter time Filter Input Signal

6 Fhase Filter

-6 Consecutive Filter

Inputs differ from Filter Output

FIG. 3

FIG. 4

FIG. 5

FIG. 6

546 XEROX DISCLOSURE JOURNAL - Vo1.18,No. 5 September /October 1993

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Page 3 of 8

APPARATUS FOR DEBOUNCING SIGNALS(Cont'd)

FIG. 7

Filter Input Signal Filter Output Signal Bounce

Time

NG. 11 4 Lockout

Filtertime

NG.

FIG. 10

4 Lockout

Filtertirne

'

Filter Input Signal

U 17

Filter Output Signal

I

'

XEROX DISCLOSURE JOURNAL - Vol.18,No. 5 September/October 1993 547

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Page 4 of 8

APPARATUS FOR DEBOUNCING SIGNALS(Cont'd)

Filter Input Siqnal

Increment

Count FIG. 12

 Filter InDut Sianal -111 I I I I

~-

Counter = Max

Signal Output Filter 6PhaseFilter T 1 1 1 1 1

FIG. 13 6 Consecutive Filter Outputs differ from Filter Inputs

FIG. 14

FlG. 9

FIG. 15 FIG. 16

548 XEROX DISCLOSURE JOURNAL - V01.18,No. 5 September /October 1993

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Page 5 of 8

APPARATUS FOR DEBOUNCING SIGNALS(Cont'd)

Debounce and lockout filters for simultaneously processing multiple noisy signals to produce multiple corresponding debounced signals are disclosed. More specifically in Figure 1, filter 20 includes input part 22, processor 24, output part 26 and memory 28. Inputs to the filter processor are a plurality of voltage signals Vl-VN. Outputs from filter 20 include filtered signals Fl-FN. Inputs V1-VN are produced by switch circuits 10. Input voltages V1-VN are provided to corresponding gates GI-GN. Sampling signal TM is provided to each of the gates GI-GN to produce binary signals B1,M-BN7M. Signals B1,%- BN,M constitute a plurality of binary signals having a sequence of values indexed on index designator M. A current value from each of the plurality of binary signals is provided to register 32 where the plurality of current values are retained until read in by processor 24. Preferably input part 22 is part of a microprocessor comprised of input part 22, processor 24 and output part 26. A multiplexer may be advantageously interposed between switch circuits 10 and input part 22 to select between multiple sets of switch voltage V. The value of each signal at a point in time is either in an ON state or an OFF state (logical "1" or logical "0"). Figure 2 shows a filter input signal changing states several times before finally remaining in one state. Figure 2 also shows a debounced filter output signal switching to its output state after the debounce filter time.

Using the microprocessor bas...