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DUAL ARBITERS FOR EFFICIENT BUS ARBITRATION

IP.com Disclosure Number: IPCOM000026878D
Original Publication Date: 1994-Feb-28
Included in the Prior Art Database: 2004-Apr-06
Document File: 2 page(s) / 104K

Publishing Venue

Xerox Disclosure Journal

Abstract

Large digital system incorporating different VLSI chips (e.g., CPUs, DMA Controllers), which may each become a bus master, may introduce arbitration delays that reduce the overall bandwidth of a bus. Furthermore, the lack of consistency in chip manufacturers bus requestlgrant and clocking schemes only exacerbat the problem. Standard bus requestlgrant facilities provided by many of the devices result in idle time on the system bus while the new master synchronizes to the latest bus grant received. For example, in some direct memory access (DMA) applications, where only a few bytes are transferred per DMA request, the idle arbitration time can be as great as the time taken to perform the transfer.

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XEROX DISCLOSURE JOURNAL

DUAL ARBITERS FOR EFFICIENT BUS ARBITRATION U.S. C1.361/407 Joseph A. Freiburg

Proposed Classification

Int. C1. HOlr 9/00

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-CENTRAL BUS ARBITER

XEROX DISCLOSURE JOURNAL - Vol. 19, No. 1 January/February 1994 83

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DUAL ARBITERS FOR EFFICIENT BUS ARBITRATION(Cont'd)

Large digital system incorporating different VLSI chips (e.g., CPUs, DMA Controllers), which may each become a bus master, may introduce arbitration delays that reduce the overall bandwidth of a bus. Furthermore, the lack of consistency in chip manufacturers bus requestlgrant and clocking schemes only exacerbat the problem. Standard bus requestlgrant facilities provided by many of the devices result in idle time on the system bus while the new master synchronizes to the latest bus grant received. For example, in some direct memory access (DMA) applications, where only a few bytes are transferred per DMA request, the idle arbitration time can be as great as the time taken to perform the transfer.

Referring to the figure, the two arbiter system illustrated will help to improve the situation described above. Rather than use the standard bus requestlgrant lines, the system allows the Master's bus grant line (BG) to be constantly asserted. This places the Master in a state where it believes that it currently controls the bus. When the Master needs to perform an actual bus access, it will immediately begin a cycle. A local fi...