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A SILICON JUNCTION FIELD EFFECT TRANSISTOR WITH A MODIFIED GATE FOR USE IN A CMOS PROCESS WITH NEGATIVE AND POSITIVE POWER SYSTEMS

IP.com Disclosure Number: IPCOM000027270D
Original Publication Date: 1996-Feb-29
Included in the Prior Art Database: 2004-Apr-07
Document File: 4 page(s) / 145K

Publishing Venue

Xerox Disclosure Journal

Abstract

In order for a JFET to function properly it must be reverse biased. This means that a single JFET can not have a negative voltage on the source and a positive voltage on the drain, or conversely, a positive voltage on the source and a negative voltage on the drain. If a JFET is biased using either a negative voltage on the source and a positive voltage on the drain or a positive voltage on the source and a negative voltage on the drain either the gate-source junction or the gate drain junction will become forward biased and the JFET will not operate correctly. A modified gate has been designed to allow negative to positive voltages across a single JFET. Additionally, this new JFET can handle voltages greater than 5 volts and is suitable for high voltage applications. This new JFET can also be used with standard CMOS cell libraries with the introduction of a p-well module.

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XEROX DISCLOSURE JOURNAL

A SILICON JUNCTION FIELD EFFECT TRANSISTOR WITH A MODIFIED GATE FOR USE IN A CMOS PROCESS WITH NEGATIVE AND POSITIVE POWER SYSTEMS Jaime Lerma

Proposed Classification

U.S. C1.257/272 Int. C1. HOlL 29/80

vG2 vss

26 24

(P+J ( n+ n+

\ - 14

12

-

10

-

I 1

VSS

XEROX DISCLOSURE JOURNAL - Vol. 21, No. 1 January/February 1996 7

[This page contains 1 picture or other non-text object]

Page 2 of 4

A SILICON JUNCTION FIELD EFFECT TRANSISTOR WITH A MODIFIED GATE FOR USE IN A CMOS PROCESS WITH NEGATIVE AND POSITIVE POWER SYSTEMS (Cont'd)

FIG. 2

vG1 vss

g3

vG2

4

26 24 30

(P+) n+ n+

14

\ I

-

Q2 -

10

-

b

vss FIG. 3

8 XEROX DISCLOSURE JOURNAL - Vol. 21, No. 1 January/February 1996

[This page contains 1 picture or other non-text object]

Page 3 of 4

A SILICON JUNCTION FIELD EFFECT TRANSISTOR WITH A MODIFIED GATE FOR USE IN A CMOS PROCESS WITH

NEGATIVE AND POSITIVE POWER SYSTEMS (Cont'd)

In order for a JFET to function properly it must be reverse biased. This means that a single JFET can not have a negative voltage on the source and a positive voltage on the drain, or conversely, a positive voltage on the source and a negative voltage on the drain. If a JFET is biased using either a negative voltage on the source and a positive voltage on the drain or a positive voltage on the source and a negative voltage on the drain either the gate- source junction or the gate drain junction will become forward biased and the JFET will not operate correctly. A modified gate has been designed to allow negative to positive voltages across a single JFET. Additionally, this new JFET can handle voltages greater than 5 volts and is suitable for high voltage applications. This new JFET can also be used with standard CMOS cell libraries with the introduction of a p-well module.

Figure 1 shows a cross-section of a JFET 8. The JFET 8 is built on a p-type substrate 10. There are two large wells, a n-well12 and a p-welll4. The p- well 14 is built within the n-welll2. The p-well14 forms the p-channel for the JFET 8. The JFET 8 is a p-channel...