Browse Prior Art Database

Method for Combinatoric Interrupt Coalescing

IP.com Disclosure Number: IPCOM000027475D
Original Publication Date: 2004-Apr-08
Included in the Prior Art Database: 2004-Apr-08
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Abstract

The core ideas of this invention are multiple ways to combine and refine interrupt coalescing algorithms to adapt them to be more suitable to different workloads and dynamically configurable based on the specific workload. This improves latency, bandwidth and CPU consumption

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Method for Combinatoric Interrupt Coalescing

Disclosed is a method to improve the interrupt coalescing algorithm by dynamically using a combination of techniques suitable to workloads on the system. Interrupt coalescing is a technique used in high bandwidth Network Interface cards(NIC) to reduce the load on Computer Central Processing Unit (CPU).

NIC developers have already recognized that there are three types of techniques [1,2,3] used to modulate this interrupt coalescing.

1. Time interval between packets determines when to interrupt, that is when the time delay between two consecutive packets exceeds a threshold,
2. quantity based, that is when the number of packets received equals or exceeds a configured limit,
3. timer based, that is when a configured time elapsed it interrupts the processor, so whatever frames have received or queue to send are processed.

It is also common to combine the Timer and Quantity algorithms for interrupt coalescing. The combination of all three algorithms does not yet exist and two algorithms for this are described in this invention to achieve customized results for various workloads.

The core ideas of this invention are multiple ways to combine and refine interrupt coalescing algorithms to adapt them to be more suitable to different workloads and dynamically configurable based on the specific workload. This improves latency, bandwidth and CPU consumption.

The first algorithm that we introduce incorporates all three of the above timers and thus improves latency. Compared to any one of the existing algorithms, this algorithm is most beneficial for systems that are not excessively CPU bound. In this instance, the administrator assigns an interrupt_interval, total packet count, and an interrupt delay (a parameter for each of the respective patents listed above). Whenever a packet arrives:

If the interrupt_interval OR total packet count OR the interrupt delay interval rules apply, then generate an interrupt.

This algorithm is an extension of the existing techniques where interrupts are generated whenever any given threshold is exceeded. In this algorithm, the total packet count represents the minimum number of packets that constitute an interesting burst. This algorithm maximizes the number of interrupts generated on any given system, while still not interrupting the CPU with each arriving packet. This is a logical choice for systems that are not heavily CPU bound and not receiving extensive peripheral interrupts.

However, consider a 2nd algorithm:

If (total packet count expires OR (interrupt delay expires AND interrupt interval expires) then generate an interrupt.

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In this algorithm, the total packet counter represents a major portion of the receive queue (for example 80-90%). In this algor...