Browse Prior Art Database

Low Dielectric Constant (Low K) Material As Spacer

IP.com Disclosure Number: IPCOM000028019D
Original Publication Date: 2004-Apr-19
Included in the Prior Art Database: 2004-Apr-19
Document File: 4 page(s) / 86K

Publishing Venue

Motorola

Related People

Olubunmi O. Adetutu: AUTHOR [+4]

Abstract

Rationale: As device features decrease with increasing technology, there is a strong need to reduce propagation delay time for high performance. Two major ways to reduce delay time are: 1. To increase drive current (Ion). However, increase in Ion implies increase in active power consumption. This means devices will operate hotter.

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Low Dielectric Constant (Low K) Material As Spacer

Olubunmi O. Adetutu, Hsing Tseng, Wei Wu and Yolanda Musgrove


Low Dielectric Constant (Low K) Material As Spacer

Rationale: As device features decrease with increasing technology, there is a strong need to reduce propagation delay time for high performance.

Two major ways to reduce delay time are:

1. To increase drive current (Ion). However, increase in Ion implies increase in active power consumption. This means devices will operate hotter.

2. The second method is to reduce Capacitance (i.e Miller Capacitance). Miller Capacitance can be broadly divided into three: a) Cof-Outer fringing, b) Cov-Overlap and c) Cif-Inner fringing. As device features shrink and gate length is reduced (Lgate), Miller capacitance becomes increasingly important, since these capacitance do not scale with gate length (Lgate): First, Cof depends on height of gate, device width and the spacer properties. Second, Cov increases as thickness of the gate dielectric is reduced and increase lateral diffusion of the S/D extensions under the gate. Third, Cif increases with increase junction depth and doping. In addition, the impact of high Miller Capacaitance on circuits can not be overstated. The Miller Capacitance multiplies during inverter switching, which slows down digital circuit and increases dynamic power consumption (see fig. 1). For analog circuits, Miller capacitance contributes to a pole in the frequency response of a MOSFET. The gain of static CMOS at high frequency is much smaller than DC gain because of this pole. As a result, Gain-Bandwidth product is reduced when miller capacitance is increased as shown in fig. 2. A strong need therefore remains to reduce miller capacitance as feature sizes decrease.

Proposal: We propose a low dielectric constant liner together with a low K spacer, such that the low K liner has good etch selectivity to the gate spacer. The low K liner may or may not be of a porous material. We define l...