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Power Reduction In Trace-back Unit Using Orthogonal Memory Bank

IP.com Disclosure Number: IPCOM000028022D
Original Publication Date: 2004-Apr-19
Included in the Prior Art Database: 2004-Apr-19
Document File: 7 page(s) / 58K

Publishing Venue

Motorola

Abstract

A technique to address the problem of power wasted in accessing bits known a priori to be irrelevant to the trace-back process by selectively isolating portions of the memory where the trace-back bit is stored. This is done by orthogonally splitting the memory into smaller banks so that only required bank is enabled during the trace-back to minimise power.

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Power Reduction In Trace-back Unit Using Orthogonal Memory Bank

Mohit K. Prasad, Arnab K. Mitra, Nitin Vig, Gaurav Davra, Amritpal Singh

Abstract

A technique to address the problem of power wasted in accessing bits known a priori to be irrelevant to the trace-back process by selectively isolating portions of the memory where the trace-back bit is stored. This is done by orthogonally splitting the memory into smaller banks so that only required bank is enabled during the trace-back to minimise power.

1. Introduction

Traceback is an operation in decoding or equalization that requires storage of large number of very wide words in a traceback RAM. Each word is composed of multiple decision bits. Each decision bit is a hypothetical decoded bit corresponding to the transition between subsequent states of the decoder or the equalizer. To reconstruct the decoded sequence a state with the minimum (or maximum) metric is picked at a particular instant. This time instant corresponds directly to the word address in the traceback RAM. The state is translated to a memory address corresponding to a decision bit that could corresponds to the most likely decoded or equalized sequence. After the single decision bit is read from the memory a new state is constructed using the bit which is used as the bit address of the previous word. This process is continued for steps for all stages of a trellis in a frame of size and traceback length . Each such iteration yields one decoded bit. At the end of the frame bits are decoded at one shot to give a total of decoded or equalized bits. The number of bits in a memory word is equal to the number of states which is given by where is the constraint length of the encoder. During the traceback process the hardware reads words each of bits to read bits. If conventional memory with a word size of is used then all bits have to be read over the entire frame. As each word is read, the state address is used to pick the single bit of interest. Thus despite the fact that only of bits is used, the conventional memory access expends as much power as if all are used.

This idea addresses the problem of power wasted in accessing bits known a priori to be irrelevant to the traceback process by selectively isolating portions of the memory where the traceback bit is stored. The idea may be extended to applications where large memory words are addressed and it is known a priori that the information of interest is embedded within a known portion of the memory word.

1.1 Criteria for selecting Traceback RAM

Traceback requires the storage of a large number of data of wide width, which depends on the maximum constraint length supported. To read/write a word from the memory all the drivers of the storage elements in that row are charged. In the traceback only one bit is required to be read at a time. In the case of one 64X64 memory block for each read access full 64-bit word would have to be accessed for one bit. So for a typical memory the driver ...