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Address Maps for Bus to Bus Bridges: Assignment and Resolution

IP.com Disclosure Number: IPCOM000028038D
Original Publication Date: 2004-Apr-21
Included in the Prior Art Database: 2004-Apr-21
Document File: 6 page(s) / 173K

Publishing Venue

IBM

Abstract

This article provides a method to automate address map assignment and address resolution for bus-to-bus bridges in a architectural simulation model for a multi-bus system. Anytime the system has multiple buses with a master on one bus capable of exchanging data with a slave on a different bus using bus-to-bus bridges, there is a redundancy in the address map assignments. This redundancy arises because the bridge provides a gateway to all the slaves on another bus. The address map of the bridge is therefore the combined address ranges of all the slaves on the destination bus. Therefore, requiring the user/modeler to enter the slave address map for the bridge into the configuration files, is undesirable. Firstly, it becomes an unnecessary overhead for the user to create this slaves address map since it can be easily calculated from the slaves on the destination bus. Secondly, it is prone to errors while entering the data, which require a consistency check in the model.

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Address Maps for Bus to Bus Bridges: Assignment and Resolution

The address map of each slave device could simply be a two-tuple with the start and end address of its range. It could also be a list of such two tuples if the address map is non-contiguous.

    When there are multiple buses that allow a master on one bus to talk to a slave on another, there is usually a bridge connecting the buses. Fig. 1 shows a two-bus system example. There are two bridges in the figure, one going from Bus A to Bus B and another going in the reverse direction. The address map for the bridges can be specified in two ways:

  Firstly, the bridge's address map may be specified by the modeler/user in the configuration file

           Secondly, a pointer to (in the form of a unique name) the bus that the bridge connects to is specified by the modeler/user. This invention describes a new technique to implement the second option. The invention implementation suggests that the configuration files describing the masters and slaves on a bus be constructed such that the bridge slave is always the last slave in the configuration file list. This is just to speed up the search during simulation run time.

    Every bus in the system has its own configuration file. This is not necessary, but in this disclosure separate configuration files for each bus are assumed. Each bus has a unique name to identify it with. All slaves except the bridge slaves define their address maps in their associated list of properties in the configuration files. The bridge slaves only list the name of the bus that they will connect their parent bus to and the filename of the configuration file for that bus. A global table is maintained with the name of the buses that have started being constructed, and a pointer to the linked list holding the address map of the bus. This global data structure is illustrated in Fig. 2.

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Figure1: An Example two-bus system with bridges connecting the buses

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INDEX BUS NAME Pointer

Bus Address Map Table Format = (index, unique bus name, pointer to linked list of its slave address map)

  Linked List Entry Format = (start address, end address, DestBusName, Next Pointer)

Figure 2: Global system address map structure after model construction phase

Figure 2 shows how the entry in the linked list of address maps for each slave device on a bus looks. The non-bridge slaves have the start and end addresses of their address map, a NULL string for the Destination bus name, and the pointer to the next element in the linked list. The bridge slaves have zeros for the start and end addresses of their map, the name of the bus that they point to and the pointer to the linked list of the destination bus' address map.

The model construction method (during system bring-up before simulation): The construction begins with the first bus. There is always a notion of building up the system model with a primary bus in the system....