Browse Prior Art Database

Staggering the Reset-to-Memory Array in a Memory Sub-System to Eliminate Power Surges

IP.com Disclosure Number: IPCOM000028041D
Publication Date: 2004-Apr-21
Document File: 2 page(s) / 16K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that staggers resets on a rank-by-rank basis to eliminate power surges.

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Staggering the Reset-to-Memory Array in a Memory Sub-System to Eliminate Power Surges

Disclosed is a method that staggers resets on a rank-by-rank basis to eliminate power surges.

Background

A reset pin is defined for DDR3 to simplify DRAM initialization. A single reset pin is routed on all memory devices in the system. This causes a power surge during the reset operation; for example, if all devices execute a “pre-charge all” command internally at the same time, then there will be a power surge.

Currently, there is no reset pin on the DRAM. The memory controller has to initialize each rank using a complicated initialization sequence. If there are errors in the system there is no easy way to recover from them.

General Description

The disclosed method staggers resets on a rank-by-rank basis to eliminate power surges. Figure 1 shows the reset timings for DDR3. Reset is asserted asynchronously for x clocks for it to be recognized as a valid reset operation. The clocks and voltages must be stable for y clks before the de-assertion of reset, with y=~200us. The memory controller cannot issue a reset during self-refresh (i.e. S3 state).

When a reset is asserted, any operation is aborted in the DRAM and the register set (MRS) is reset to the default state . The internal refresh counters are reset, and the programmable output impedance is reset to mid-point. The DLL state machine is also reset. The reset is de-asserted asynchronously to the clock, and synchronized internally in t...