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Input Buffer Circuit for High Voltage Tolerant I/Os Using Low Voltage Tolerant Transistors

IP.com Disclosure Number: IPCOM000028042D
Publication Date: 2004-Apr-21
Document File: 2 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a circuit for a 5V tolerant I/O input buffer, which separates the propagation path of the high and low voltages and protects the MOS devices without noise margin impacts.

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Input Buffer Circuit for High Voltage Tolerant I/Os Using Low Voltage Tolerant Transistors

Disclosed is a method that uses a circuit for a 5V tolerant I/O input buffer, which separates the propagation path of the high and low voltages and protects the MOS devices without noise margin impacts.

Background

To design the 5V tolerant I/Os, three main problems must be addressed:

1.      Overstress of the MOS devices must be avoided.

2.      Leakage from the pad pin must be avoided.

3.      Input noise margins must be large enough for safe operation.

The disclosed method solves all of these problems without the need for an additional power supply, and without any DC current path at the steady-state condition.

General Description

The disclosed method uses a circuit for a 5V tolerant I/O input buffer, which separates the propagation path of the high and low voltages and protects the MOS devices without noise margin impacts. The circuit is designed using a single high voltage (i.e. 3.3V) power supply.

The attached circuit, which is used for a 5V tolerant I/O with 2.5V tolerant transistors, can also be used with minor changes for low-voltage technology when high-voltage tolerance is needed.

Figure 1 shows the disclosed method when the circuit receives the 5.5V, and translates it to the low voltage domain. In this configuration, the Nbias is used to protect the NMOS devices from the high input voltage, while the Pbias is used to protect the PMOS devices from the high power supply voltage.

Figure 2 sho...