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Configurable Microprocessor Branch Prediction for Performance and Power Savings

IP.com Disclosure Number: IPCOM000028112D
Original Publication Date: 2004-Apr-26
Included in the Prior Art Database: 2004-Apr-26
Document File: 4 page(s) / 98K

Publishing Venue

IBM

Abstract

This article introduces new techniques for implementing branch prediction mechanisms in a microprocessor design. These techniques provide ways to reduce power and provide a programmable configuration that can be used to increase performance and reduce the impact of the overall complexity.

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Configurable Microprocessor Branch Prediction for Performance and Power Savings

Microprocessor design has become increasingly complex and competitive while the designs are constrained by schedule, performance, area and power. One widely implemented function for gaining performance is branch prediction. With microprocessor pipelines growing in size, microprocessor designs are finding it necessary to perform some type of branch prediction. Described below are branch prediction techniques that the design used and expanded on to provide higher performance, reduced power and flexibility for debug.

    A common component of all branch prediction schemes is the branch history table (BHT). The BHT is typically an array used to save and track the history of previously executed branches. If a branch with a given address is predicted taken, a count value inside the BHT is incremented to identify that the branch is more likely to be taken than not taken. Conversely, if the branch is not taken then the count value is decremented. The next time the branch is executed, the BHT information is used to predict the branch direction. If the count value is high or above a threshold then the branch is predicted to be taken otherwise it is predicted to be not taken.This method relies on the fact that most branches follow a regular pattern whereby they are usually taken or not taken.

    By adding a Global History Register (GHR) to the BHT design the execution state of branches can be tracked relative to the instruction path that led up to the branch. In other words, a branch may change from usually taken to usually not taken depending on the branch path that led up to it. The GHR also helps reduce "hot spots" in the BHT that are accessed by multiple branches. The benefit of a GHR based design is dependent on the programs that are run but in general the performance impact is positive.

    The design uses a traditional BHT array along with a GHR register to form a GShare type design as shown in Figure1. A unique function of the design is that the BHT can be completely disabled by a software write to a configuration register (mtspr). When this is done, all branches are predicted based purely on the type of branch instruction. Thus, operational correctness is not lost but but the prediction mechanism is changed. Disabling the BHT can be used to reduce power, provide application specific performance increase or to provide bug fixes. The BHT can also be disabled while the processor is running without disturbing operational correctness. This function can be used by the software application to turn the BHT on and off during certain code sequences allowing power savings or performance increases.

    The GHR register in the design can also be disabled through software control. This allows the BHT to follow a purely static approach rather than GShare whereby the branch history is removed from the BHT accesses. In other words, every branch is predicted taken or not taken based pur...