Methods and Apparatus for Common Mode Calibration and Compensation
Publication Date: 2004-Apr-26
The IP.com Prior Art Database
A calibration and/or compensation method and related apparatus for improving communication between integrated circuit devices. The apparatus includes a digital to analog converter that introduces an offset that is superimposed on a transmitted signal to shift the operating parameters of the communicated signal. In an embodiment, communication between two integrated circuit devices that use different termination voltages is improved.
1. Descriptive Title : Method and Apparatus for Common Mode Calibration and Compensation
2. Problem : Scaling of ICs signaling termination voltages lag behind that of scaling of process voltages.
ICs of different process generations may not allow reliable communication between themselves, with one common signal termination voltage, because of prohibiting maximum operating voltage, a side effect of scaling of process generation. (or processes from different foundry. See figure 1) UNLESS
a) We are to use slow and cumbersome level shifting technique (and suffer some performance degradation (like added latency, signal attenuation,... see sect. 6)
b) OR we could manipulate the data signal, 'common mode' compensate it to a different voltage domain, all within the safe operating voltage range of the receiving IC and allow it to process data directly without adding delay or affecting signal quality as per level shifting technique.
3. Solution: An IC calibration technique consisting of a transmitters, receivers, current DACs, ODTs, are used to monitor the source and destination termination voltages and precisely introduced a balanced DC offset that, when superimposed on the transmitting AC signal will fall well into the maximum operating condition of the destination IC allowing reliable communication between ICs that are processed from different foundries or different process generations.
a)First we want to sense the two power supply domains to determine the differences in termination voltages (refer to Figure 2, example 2). Select TX1, ODT2 to be off while ODT1 is still enable; doing this will allow Vterm1 to be available for sensing at RX2. Select the appropriate mux to allow Vterm1 and Vterm2 to be sampled by RX2 and DAC code controlled current sources to reach
1.2V Max Vdd
for 0.13um process Figure 1
1.0V Max Vdd
for 0.09um process
equilibrium. In some case this could the secondary ESD protection as required, or the local TX by equally splitting it into 2 identical halves in bi-directional IC.
The offset compensating required current "I=(Vterm1-Vterm2)/(Resd+Rodt/2)" is directly proportional to the amount of offset needed and there is NO performance degradation, in term of added delay and attenuation of data voltage because this 'balanced offset' is outside of the critical data path. One may argue that there is a DC current across the channel. Equalization also put DC current on the channel but is extremely helpful for improved signaling. So that one should carefully consider the pro and con for each application.
We now have a "controlled offset common mode voltage" created by the destination IC to shift the data signal that will be transmitted on top of this DC voltage to safely arrive at the RX destination to be sampled (see simulation data).
b) Circuitry that follows the "ESD resistors" can be of high speed regular devices that translate to smaller Ci...